US 5,350,704 A · Method of making adaptive configurable gate array by using a plurality of alignment markers

Abstract

A new configurable gate array is defined in a master slice wafer form without borders of the kind currently known between constituent transistor gates, effectively providing a sea of gates over the wafer, interrupted if at all by islands, containing markers or the like; and a resultant application specific integrated circuit formed of such master slice is defined. In the IC, transistor gate cells, which are the same type of cells used for other purposes in the IC, are configured to serve the input and output function. Accordingly, the input and output function may be placed on any location in the IC. As an incident to personalization of the wafer saw lanes are formed of channels that extend over transistor cells and the latter cells are consequently destroyed in slicing the wafer. Means are also disclosed for an improved E-beam lithographic apparatus which permits an IC chip to be placed on an area of a wafer that is occupied by a marker, providing a wiring or macro design that avoids the marker.

Claims3

Dependent claims

In the process of fabricating integrated circuits on a semiconductor wafer containing alignment markers on a surface thereof in which the integrated circuits are to be formed through exposure of the semiconductor wafer using a controlled beam of energy applied by a beam control means apparatus capable of positioning said energy beam to any position on said surface;

said beam control means including software program means containing initially stored information defining a circuit pattern and means for controlling the on and off status of said beam to energize the beam only at selected coordinate locations on said surface of said semiconductor wafer where said circuit pattern is to be formed, the improvement comprising the steps of:
determining the positions of said alignment markers on said surface or said semiconductor wafer;
determining if any of said alignment markers coincide with said initially stored circuit pattern on said semiconductor surface indicating an overlap;
defining an alternative mapping of said initially stored circuit pattern to produce a revised circuit pattern that is functionally equivalent to said initially stored circuit pattern without overlapping areas of said surface occupied by said alignment markers;
and exposing said surface according to said alternative mapping of said circuit pattern.

2 more elements

The process of masking a semiconductor wafer in the fabrication of an integrated circuit chip, wherein said wafer includes a plurality of alignment markers located at spaced coordinate positions on the surface thereof and in which there is provided an initial integrated circuit design in digital form defining a mask, and in which a controlled beam means directs a controlled beam of energy at the wafer to form a circuit design pattern on the wafer in accordance with an integrated design stored in a digital form in a memory, which includes the steps of:

(a) calculating the coordinates of the integrated circuit design initially provided and storing such initial coordinates in memory as the initial design initial coordinates;
(b) calculating the coordinates of the markers and storing the number and coordinates of said markers, said coordinates being arranged in a priority order with the marker at one distal end of the wafer right or left side and top or bottom first in order then those along the same row and continuing to the next row, row by row in sequence, with any marker at the diagonally opposite side of the wafer being last in said order;
(c) retrieving the coordinates of said first marker in said priority order;
(d) checking to determine if there exists a revised set of coordinates of said integrated circuit design stored in memory and, (e1) if such exists, retrieving said revised set of coordinates, or, alternatively, (e2) if such revised set does not exist, retrieving said initial set of coordinates;
(f) comparing the coordinates of the retrieved marker with the retrieved coordinates of said integrated circuit design and, (g1) if no portions thereof are the same, checking to determine if there are any remaining markers in said order that have not been tested and, if such untested marker exists, (g2) retrieving the next remaining untested marker in said order and (g3) iterating the preceding comparison or, alternatively, (h1) if some portions of the coordinates of the retrieved marker and that of the integrated circuit design are the same, indicative of an overlap, (h2) setting a coordinate revision flag, indicating the existence of an overlap between said two sets of coordinates and the need for revision of the coordinates of the integrated circuit design and (h3) thereafter initiating the next check step;
(i) checking to determine the existence of a coordinate revision flag;
(j) in the event of a negative result to said flag check of step (h), checking to determine if revised coordinates were stored on the integrated circuit design;
and
(k) in the event of a negative result to said last named step (j), (k1) retrieving said original design coordinates;
and (k2) initiating operation of said controlled beam means to apply the retrieved integrated circuit design to said wafer;
and
(1) in the event of a positive result to said step (i), revising the coordinates of the integrated circuit design to avoid the coordinates occupied by the last tested marker, including the step of lowering a portion of the design from the row in which like coordinates are present by one row in said gate array;
(11) storing the coordinates of the revised integrated circuit design, replacing any prior revisions thereof as may exist in storage;
(13) resetting said flag;
and (14) checking to determine whether there remain any markers in said order that have not been compared to coordinates of the integrated circuit design;
and
(m) in the event of a positive result to said last named step (14), (m1) retrieving the next marker remaining in said order and (m2) iterating the comparison process step following retrieval of such marker, commencing at step (d) or, alternatively, (n) in the event of a negative result to said last named step (14) checking to determine the existence of a revised coordinates of said integrated circuit design;
and
(o1) upon positive determination of said last named step (n) retrieving said revised coordinate design in lieu of the initial coordinate design or, alternatively, (o2) upon a negative determination of said last named step (n) retrieving said original design coordinates;
and
(p) initiating operation of said controlled beam means to apply the retrieved integrated circuit design to said wafer;

18 more elements

Dependencies are inferred from the claim text.

Method of making adaptive configurable gate array by using a plurality of alignment markers

Life of this patent

Method of making adaptive configurable gate array by using a plurality of alignment markers

Life of this patent

Abstract

Claims3