US 5,350,662 AGranted

Maskless process for forming refractory metal layer in via holes of GaAs chips

AssigneeHughes Aircraft Company

InventorTom Y. Chi

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Abstract

A "maskless" process is provided for the formation of a refractory metal layer (22b), such as titanium, in via holes (18) through GaAs wafers (12) to contact microwave monolithic integrated circuit (MMIC) devices (10) formed on the front surface (12a) thereof. The process of the invention, which prevents AuSn solder (28) from filling up the holes during a subsequent eutectic AuSn bonding of the device to a metal carrier (30), such as molybdenum, utilizes the difference of resist thickness on the GaAs backside surface (12b) and in the via holes, so that the resist (24b) remaining in the via holes after removing the resist (24a) over the GaAs back surface serves as a mask in etching the refractory metal layer (22a) over the GaAs back surface. The process of the invention does not require any masks, and results in self-alignment of the refractory metal to the via hole. The process is simple and results in high yield of the MMIC devices on GaAs chips (26).

Claims12

Dependent claims

A method for providing contacts to microwave monolithic integrated circuit devices formed on a gallium arsenide wafer, said gallium arsenide wafer having a front and a back surface wherein (1) at least one via hole is formed from said back surface of said wafer through to said front surface of said wafer to expose a portion of each said device, (2) a metal layer is formed on said back surface and in each of said via holes, thereinto (3),each of said devices subsequently bonded to a metal carrier using a AuSn solder alloy, contacting said portion of each said device, said method comprising the steps of:

(a) forming a layer of a refractory metal lining each of said via holes,
(b) blanket-depositing a layer of said refractory metal on said metal layer, including in said via holes;
(c) forming a positive resist layer on said refractory metal layer and filling said via holes with said resist layer;
(d) baking said resist layer;
(e) exposing all of said resist layer to ultraviolet radiation in the absence of any mask layer;
(f) developing said resist layer to remove all of said resist layer lying over said back surface, leaving said resist layer in said via holes to thereby uncover portions of said refractory metal layer over said back surface;
(g) removing said uncovered portions of refractory metal over said back surface;
and
(h) removing said resist layer remaining in said via holes, leaving said refractory metal lining said via holes, wherein said refractory metal layer is selfaligned to said via holes to prevent the intrusion of said AuSn solder.

6 more elements

A process for providing contacts to microwave monolithic integrated circuit devices formed on a gallium arsenide wafer, said gallium arsenide wafer having a front surface and a back surface wherein (1) at least one via hole is formed from said back surface of said wafer through to said front surface to expose a portion of each said device, (2) a metal layer consisting essentially of a titanium/platinum/gold multistructure is formed on said back surface and in each of said via holes, contacting said portion of said device, and (3) each said device is subsequently bonded to a metal carrier using a AuSn solder alloy, wherein said process comprises, prior to step (3):

(a) blanket-depositing a layer of titanium ranging from about 500 to 1,000 .ANG. in thickness on said metal layer, including in said via holes;
(b) forming a positive resist layer on said titanium layer and filling said via holes;
(c) baking said resist layer;
(d) exposing all of said resist layer to ultraviolet radiation in the absence of any mask layer;
(e) developing said resist to remove all resist lying over said back surface but leaving resist in said via holes to thereby uncover portions of said titanium layer over said back surface;
(f) removing said uncovered portions of titanium over said back surface;
and
(g) removing said resist remaining in said via holes, leaving said titanium lining said via holes, wherein said titanium layer is self-aligned to said via hole to prevent the intrusion of said AuSn solder thereinto.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/181,371Filed 13 Jan 1994 · continuation
Priority: 26 Mar 1992
Granted: 27 Sep 1994
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10P 76/2041
Of organic photoresist masks: photolithographic processes
G03F 7/2022
Exposure; Apparatus therefor: multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g.…
H10W 20/0234
The interconnections being through-semiconductor vias: comprising etching via holes that stop on pads or on electrodes
H10W 20/0242
The interconnections being through-semiconductor vias: comprising etching via holes from the back sides of the chips, wafers or substrates

Family

Serial857,902Parent of this continuation · filed 26 Mar 1992
US 5,350,662 AThis patent

From the US filing history. Foreign family members aren’t listed.

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