Selective call receiver having CMOS power-on reset circuit

A selective call receiver powered by a battery supplying a first voltage, the selective call receiver including a voltage multiplier that generates a second voltage from the first voltage, the selective call receiver comprising:

• a receiver that provides a received signal;
• a demodulator that recovers an information signal from the received signal;
• an address correlator that correlates a recovered address contained within the information signal with a predetermined address corresponding to the selective call receiver, and in response to said recovered and predetermined addresses substantially correlating, the address correlator generates a detect signal indicating selection of the selective call receiver;
• a processor that in response to the detect signal, extracts message information contained within the information signal for presentation, the processor operating from the second voltage;
• and
• a power-on reset circuit coupled to the processor for generating a power-on reset signal comprising a processor reset and a processor execute state, the power-on reset signal changing from the processor reset to the processor execute state when the second voltage exceeds a sum of a PMOS transistor threshold voltage and a NMOS transistor threshold voltage, thereby completing a power-on reset of the processor indicating availability of the second voltage for powering the processor, the power-on reset circuit comprising:
• a first PMOS transistor having a first terminal coupled to the first voltage and to a control terminal of a first NMOS transistor, the first PMOS transistor further having a control terminal coupled to a ground reference and a second terminal providing the first portion of the power-on reset signal;
• a second PMOS transistor having a control terminal and a first terminal coupled to a first terminal of the first NMOS transistor, the second PMOS transistor further having a second terminal coupled to the second voltage, and the first NMOS transistor further having a second terminal coupled to a ground reference, the second PMOS transistor having the PMOS transistor threshold voltage;
• and
• a second NMOS transistor having a control terminal coupled to the first terminal of the first NMOS transistor, a second terminal coupled to the ground reference, and a first terminal providing the second portion of the power-on reset signal, the second NMOS transistor having the NMOS transistor threshold voltage.

A selective call receiver that operates to recover an information signal and is powered by a battery supplying a first voltage that is multiplied to generate a second voltage, the selective call receiver comprising:

• a processor that extracts message information contained within the recovered information signal for presentation, the processor operating from the second voltage, the processor including a power-on reset circuit that generates a power-on reset signal comprising first and second portions corresponding with a processor reset and a processor execute state, respectively, the power-on reset signal changing from the processor reset to the processor execute state when the second voltage exceeds a sum of a PMOS transistor threshold voltage and a NMOS transistor threshold voltage, thereby completing a power-on reset of the processor, the power-on reset circuit comprising:
• a first PMOS transistor having a first terminal coupled to the first voltage and to a control terminal of a first NMOS transistor, the first PMOS transistor further having a control terminal coupled to a ground reference and a second terminal providing the first portion of the power-on reset signal;
• a second PMOS transistor having a control terminal and a first terminal coupled to a first terminal of the first NMOS transistor, the second PMOS transistor further having a second terminal coupled to the second voltage, and the first NMOS transistor further having a second terminal coupled to a ground reference, the second PMOS transistor having the PMOS transistor threshold voltage;
• and
• a second NMOS transistor having a control terminal coupled to the first terminal of the first NMOS transistor, a second terminal coupled to the ground reference, and a first terminal providing the second portion of the power-on reset signal, the second NMOS transistor having the NMOS transistor threshold voltage.