Control circuit for digital data transfer

A control circuit for digital data transfer between first and second digital circuits which are respectively provided with different bus architectures, said first digital circuit having an N-bit data bus, N being a positive even integer, said second digital circuit having an N/2-bit data bus, said control circuit being included in said first digital circuit and comprising:

• a first data bus transceiver which is operatively coupled to said second digital circuit and to a first N/2-bit data bus provided in said first digital circuit, said first data bus transceiver being assigned to pass therethrough first N/2-bit data;
• a second data bus transceiver operatively coupled to said second digital circuit and to a second N/2-bit data bus provided in said first digital circuit, said second data bus transceiver being assigned to pass therethrough second N/2-bit data;
• first memory means for storing said first N/2-bit data applied from said second digital circuit via said first data bus transceiver, said first memory means being coupled to said first data bus transceiver via said first N/2-bit data bus;
• second memory means for storing said second N/2-bit data applied from said second digital circuit via said second data bus transceiver, said second memory means being coupled to said second data bus transceiver via said second N/2-bit data bus;
• first control means operatively coupled to said first and second data bus transceivers, said first control means controlling said first and second data bus transceivers so as to determine data transfer direction between said first and second digital circuits based on negotiations between said first and second digital circuits on a right of use of the data buses within said first and second digital data circuits, and said first control means selectively rendering one of said first and second data bus transceivers operative;
• second control means for allowing said first memory means to be active if said first control means renders said first data bus transceiver operative and if said first control means instructs data to be received, from said second digital circuit, and said second control means allowing said second memory means to be active if said first control means renders said second data bus transceiver operative and if said first control means instructs data to be received from said second digital circuit;
• and
• third control means for rendering said N-bit data bus to be used as an address bus in a time sharing manner, said third control means branching said N-bit data bus into said first and second N/2-bit data buses.