Programming process for 3-level programming logic devices

A process of programming a programmable logic device for carrying out a specified logic function, the programmable logic device to be programmed being of a type having multiple functional blocks, each functional block of said programmable logic device having a number of input lines, output lines and successive configurable first and second arrays between said input lines and output lines for carrying out first and second levels of logic, said programmable logic device also having input pins, output pins and a programmable interconnect matrix connected to said inputs and outputs of said functional blocks and to said input pins and output pins of said programmable logic device, said programmable interconnect matrix being configurable by means of programming so as to connect selected input pins of said programmable logic device to selected input lines of said functional blocks and to connect selected output lines of said functional blocks to selected output pins of said programmable logic device for carrying out a third level of logic, the programming process comprising:

• assigning subfunctions of a specified logic function to be programmed into said programmable logic device to particular functional blocks using apparatus other than the programmable logic device that has been provided to be programmed, said logic function being representable as a plurality of subfunctions in sum-of-products form, each subfunction having a set of product terms with a certain number of input terms,
• selecting input terms to be logically combined in said programmable interconnect matrix whenever the number of input terms required by the subfunctions assigned to a particular functional block exceed the number of input lines to that functional block, the selected input terms being those input terms which are combined to form product terms of the assigned subfunctions,
• loading said assigned subfunctions into said particular functional blocks by configuring the first array of each functional block to carry out said first level of logic such that product terms corresponding to said subfunctions are produced by said first arrays from signals on said input lines and by configuring the second array of each functional block to carry out said second level of logic such that said product terms produced by said first arrays are combined in said second arrays to produce said subfunctions at said output lines, and
• configuring said programmable interconnect matrix for carrying out said third level of logic such that input terms received from said selected input pins are logically combined in said programmable interconnect matrix to produce combined input terms connected to said selected input liens of assigned functional blocks and such that outputs from said functional blocks representing said subfunctions are logically combined in said programmable interconnect matrix to produce said logic function on said output pins.

A process of programming a programmable logic device for carrying out a specified logic function, the programmable logic device to be programmed being of a type having multiple functional blocks, each functional block having input lines, output lines and successive configurable first and second arrays between said input lines and output lines for carrying out first and second levels of logic, said programmable logic device also having input pins, output pins and a programmable interconnect matrix connected to said inputs and outputs of said functional blocks and to said input pins and output pins of said programmable logic device, said programmable interconnect matrix being configurable by means of programming so as to connect selected input pins of said programmable logic device to selected input lines of said functional blocks and to connect selected output lines of said functional blocks to selected output pins of said programmable logic device for carrying out a third level of logic, the programming process comprising:

• assigning subfunctions of a specified logic function to be programmed into said programmable logic device to particular functional blocks using apparatus other than the programmable logic device that has been provided to be programmed, said specified logic function being a multiple output function representable as a plurality of single output subfunctions in sum-of-products form, each subfunction having a set of product terms, the assigning of said subfunctions to particular functional blocks being carried out such that wherever a large subfunction exceeds a size limit of a functional block the assigning of said subfunctions splits said large subfunctional into a plurality of smaller subfunctions and assigns said smaller subfunctions to at least two separate functional blocks,
• loading said assigned subfunctions into said particular functional blocks by configuring the first array of each functional block to carry out said first level of logic such that product terms corresponding to said subfunctions are produced by said first arrays from signals on said input lines and by configuring the second array of each functional block to carry out said second level of logic such that said product terms produced by said first arrays are combined in said second arrays to produce said subfunctions at said output lines, and
• configuring said programmable interconnect matrix for carrying out said third level of logic such that said outputs from said functional blocks representing said subfunctions are logically combined in said programmable interconnect matrix to produce said logic function on said output pins.

A process of programming a programmable logic device for carrying out a specified logic function, the programmable logic device to be programmed being of a type having multiple functional blocks, each functional block having input lines, output lines and successive configurable first and second arrays between said input lines and output lines for carrying out first and second levels of logic, said programmable logic device also having input pins, output pins and a programmable interconnect matrix connected to said input lines and output lines of said functional blocks and to said input pins and output pins of said programmable logic device, said programmable interconnect matrix being configurable by means of programming so as to connect selected input pins of said programmable logic device to selected input lines of said functional blocks and to connect selected output lines of said functional blocks to selected output pins of said programmable logic device for carrying out a third level of logic, said programming process comprising:

• assigning subfunctions of a specified logic function to be programmed into said programmable logic device to particular functional blocks using apparatus other than the programmable logic device that has been provided to be programmed, said specified logic function being a multiple output function representable as a plurality of single output subfunctions in sum-of-products form, each subfunction having a set of product terms, the assigning of said subfunctions to particular functional blocks being carried out such that wherever any functional block is initially assigned a set of one or more subfunctions such that a density measure of output lines used by the assigned subfunctions is less than a predetermined threshold, the assigning further includes splitting the subfunctions assigned to that functional block so as to use more output cells,
• loading said assigned subfunctions into said particular functional blocks by configuring the first array of each functional block to carry out said first level of logic such that product terms corresponding to said subfunctions are produced by said first arrays from signals on said input lines and by configuring the second array of each functional block to carry out said second level of logic such that product terms produced by said first arrays are combined in said second arrays to produce said subfunctions at said output lines, and
• configuring said programmable interconnect matrix for carrying out said third level of logic such that said outputs from said functional blocks representing said subfunctions are logically combined in said programmable interconnect matrix to produce said logic function on said output pins.