Bidirectional FIFO with parity generator/checker

A bidirectional high speed buffered digital communication system comprising:

• a first high speed digital transceiver;
• a second high speed digital transceiver;
• a bidirectional memory buffer device including:
• a first bidirectional data port communicatively connected to said first transceiver;
• a second bidirectional data port communicatively connected to said second transceiver;
• an input multiplexer responsive to a first control signal,
• wherein when said first control signal is of a first state:
• said input multiplexer is operative to receive a series of data words from said first bidirectional data port, and output said data words;
• and when said first control signal is of a second state:
• said input multiplexer is operative to receive a series of data words from said second bidirectional data port, and output said data words;
• a byte/word converter responsive to a second control signal, wherein when said second control signal is of a first state:
• said byte/word converter is operative to receive a set of input data words, each x-bits in length, from the input mux, to construct an assembled data word, y-bits in length, where y is greater than x, by concatenating the bits of the set of input data words, and to output said assembled data word;
• and when said second control signal is of a second state:
• said byte/word converter is operative to receive input data words, y-bits in length, from the input mux, and output said input data words unchanged in length;
• a FIFO memory array responsive to a third control signal, wherein upon receipt of said third signal:
• said FIFO memory array is operative to receive a data word from the byte/word converter, to write said data word into a memory location indicated by a write pointer, and to update said write pointer to indicate the next memory location available to be written to;
• said FIFO memory array further responsive to a fourth control signal, wherein upon receipt of said fourth signal:
• said FIFO memory array is operative to read a data word from a memory location indicated by a read pointer, to output said data word, and to update said read pointer to indicate the location of the next data word to be read;
• a word/byte converter responsive to a fifth control signal, wherein when said fifth control signal is of a first state:
• said word/byte converter is operative to receive a data word from the FIFO memory array, to construct a set of disassembled data words, each containing a part of the received data word, and to output said disassembled data words;
• and when said fifth control signal is of a second state:
• said word/byte converter is operative to receive data words from the FIFO memory array, and to output said data words unchanged;
• an output mux, responsive to a sixth control signal, wherein when said sixth control signal is of a first state:
• said output multiplexer is operative to receive a series of data words from said word/byte converter, and to output said data words to said first bidirectional data port;
• and when said sixth control signal is of a second state:
• said output multiplexer is operative to receive a series of data words from said word/byte converter, and to output said data words to said second bidirectional data port;
• control logic responsive to external input signals, and operative to generate said first, second, third, fourth, fifth and sixth control signals.