Apparatus for calculating delay when executing vector tailgating instructions and using delay to facilitate simultaneous reading of operands from and writing of results to same vector register

In a vector processing computer having a plurality of vector registers which can be read and written within a same clock period, wherein the plurality of vector registers include a first and a second vector register, a method of performing vector operations comprising the steps of:

• reading in successive clock periods, successive elements of both the first and the second vector registers;
• performing a first mathematical function on the successive elements of said first and second vector registers to produce a first result vector, wherein said first mathematical function is performed in a first functional unit with a first functional unit time;
• and
• writing, in successive clock periods and after said first functional unit time, said first result vector to said first vector register;
• wherein the step of reading comprises the step of determining a vector register address used to address elements of said vector registers;
• and
• wherein the step of writing said first result vector to said first vector register comprises:
• providing a vector register address subtractor for subtracting an address offset from said vector register address to provide a vector register write address;
• determining the address offset wherein the step of determining comprises:
• calculating an elapsed time equivalent to time elapsed between issue of a first instruction that uses said first vector register as an operand and issue of a second instruction that uses said first vector register as a destination;
• determining the first functional unit time associated with said second instruction;
• and
• expressing the address offset as a function of the elapsed time and the first functional unit time, wherein the address offset is expressed in equivalent vector register write cycles;
• comparing said address offset to a vector length associated with first the instruction;
• and
• if the address offset is less than or equal to the vector length, loading said address offset into an address offset register and enabling the writing of data provided by said first functional unit to said first vector register at addresses provided by said vector register address subtractor.

In a vector processing computer having a plurality of vector registers which can be read and written within a same clock period, wherein the plurality of vector registers include a first and a second vector register, a method of performing vector operations comprising the steps of:

• reading, in successive clock periods, successive elements of both the first and the second vector registers;
• performing a first mathematical function on the elements of said first and second vector registers to produce a first result vector, wherein said first mathematical function is performed in a first functional unit with a first functional unit time;
• and
• writing, in successive clock periods and after said first functional unit time, said first result vector to said first vector register;
• wherein the step of reading successive elements of said first and second vector registers comprises providing a vector register read address counter for providing a vector register address used to address elements of said vector registers during read operations;
• and
• wherein the step of writing said first result vector to said first vector register comprises:
• providing a vector register write address counter for providing a vector register address used to address elements of said vector registers during write operations;
• providing a vector register write delay counter for delaying a write operation to one of said vector registers;
• providing a write delay equivalent to a sum of an amount of time elapsed between issue of a first instruction that uses said first vector register as an operand and issue of a second instruction that uses said first vector register as a destination and the first functional unit time associated with said second instruction, said write delay expressed in equivalent vector register write cycles;
• comparing said write delay to a vector length associated with the first instruction;
• and
• if the write delay is less than or equal to the vector length loading said write delay into said write delay counter, decrementing said write delay counter by one during each first vector register write cycle and, when the write delay counter equals zero, beginning a write operation to said first vector register.

Vector register control apparatus for a vector processing computer in which a plurality of high-speed vector registers, including a first vector register and a second vector register, are used as intermediate memory to store ordered sets of data for vector processing by one or more functional units, wherein each said vector register comprises a plurality of memory locations for storing elements of a vector and wherein the one or more functional units includes a first functional unit connected to each of the plurality of vector registers, said first functional unit comprising input means for receiving elements of a first and second vector read from said first and second vector registers, respectively, computational means for performing a mathematical function on each said vector element in a first functional unit time, wherein the first functional unit time is greater than one clock period, and output means for delivering elements of a first result vector, the apparatus comprising:

• control means, connected to said vector registers and to said one or more functional units, for transferring data between said vector registers and said one or more functional units, said control means comprising first vector control means for successively transferring elements, including a last element, read from said first vector register to said first functional unit and for successively storing elements, including a first and a last element, of said result vector to said first vector register and second vector control means for successively transferring elements, including a last element, read from said second vector register to said first functional unit and for successively storing elements, including a first and a last element, of a second result vector received from a second functional unit to said second vector register, wherein said first vector control means stores at least some of said elements of said first result vector to said first vector register concurrently with the transferring of the elements of said first and second vector registers to said first functional unit;
• wherein the first vector control means comprises a first read address counter for successively addressing elements of said first vector register during a read operation, a first write address counter for successively addressing elements of said first vector register during a write operation, a first vector length counter for indicating to said first read address counter when the last element of the elements read from the first vector register has been read, a first write vector length counter for indicating to the first write address counter when the last element of said result vector has been written to said first vector register, and a first write delay counter for delaying storage to said first vector register of the first element of said first result vector for said first functional unit time and for enabling storage, in successive clock periods, of successive elements of said first result vector to said first vector register after said first functional unit time;
• and
• wherein the second vector control means comprises a second read address counter for successively addressing elements of said second vector register during a read operation, a second write address counter for successively addressing elements of said second vector register during a write operation, a second read vector length counter for indicating to said second read address counter when the last element of the elements read from the second vector register has been read, a second write vector length counter for indicating to said second write address counter when the last element of said second result vector has been written to said second vector register, and a second write delay counter for delaying storage to said second vector register of the first element of said second result vector for a second functional unit time associated with said second functional unit and for enabling storage, in successive clock periods, of successive elements of said second result vector to said second vector register after said second functional unit time.

Vector register control apparatus for a vector processing computer in which a plurality of high-speed vector registers, including a first vector register and a second vector register, are used as intermediate memory to store ordered sets of data for vector processing by one or more functional units, wherein each said vector register comprises a plurality of memory locations for storing elements of a vector and wherein the one or more functional units includes a first functional unit connected to each of the plurality of vector registers, said first functional unit comprising input means for successively receiving elements of a first and second vector read from said first and second vector registers, respectively, computational means for performing a mathematical function on each said vector element and output means for delivering elements of a first result vector, the apparatus comprising:

• control means, connected to said vector registers and to said one or more functional units, for transferring data between said vector registers and said one or more functional units, said control means comprising first vector control means for successively transferring elements of said first vector in said first vector register and elements of said second vector in said second vector register to said first functional unit and for successively storing elements of said first result vector to said first vector register;
• wherein said first vector control means comprises:
• a vector register address counter for providing a vector register address used to address elements of said first and second vector registers;
• a vector register address offset register for providing an offset including a number of vector register write cycles equivalent to a first functional unit time, said first functional unit time being an amount of time for the first functional unit to perform said mathematical function;
• and
• a vector register address subtractor connected to said address counter and said offset register for subtracting said offset from said vector register address to provide a vector register write address that compensates for said first functional unit time during tailgating instruction that simultaneously use the first vector register as both a source and a destination register.