Microprocessor system generating instruction fetch addresses at high speed

A microprocessor system comprising:

• an arithmetic logic unit for generating flats;
• a flag update detector for outputting a flag update detecting signal;
• a status register coupled to said flag update detector and said arithmetic logic unit for receiving the flag update detecting signal and a flag outputted from said arithmetic logic unit;
• a first address outputting portion coupled to said flag update detector and said status register for receiving the flag update detecting signal, a flag outputted from said status register, a target instruction address, a next instruction address and a branch condition of a conditional branch instruction, for determining according to the flag received from said status register whether or not the branch condition is met, and for outputting first and second address candidates selected from the target instruction address and the next instruction address according to the flag update signal and to whether or not the branch condition is met;
• and
• a second address outputting portion coupled to said first address outputting portion and said arithmetic logic unit for receiving the first and second address candidates outputted from said first address outputting portion, the branch condition of the conditional branch instruction and the flag outputted from said arithmetic logic unit, for determining according to the flag received from said arithmetic logic unit whether or not the branch condition is met, and for outputting the target instruction address or the next instruction address as an instruction fetch address on the basis of a result of determining according to the flag received from said arithmetic logic unit whether or not the branch condition is met.