US 5,349,669 AGranted

Data write control means

AssigneeOki Electric Industry Co., Ltd.

InventorsYasuo Arai, Hisatake Sato

Life of this patent

Estimating the term…

Loading patent…

Abstract

The present invention relates to a data protection (310) for preventing data from being erroneously written in a data holding circuit (307). A data protection circuit (311) receives a data protection set release select signal Sa provided by a processor (330), thereby causing a second timer (316) to start timing. The data protection circuit (311) further detects the level of a chip select signal CS provided by a power supply monitoring circuit (320) after the second timer (316) timed the time interval T2 and provides a data protection signal DP corresponding to the signal Sa to the data holding circuit (307) only in the case that the data protection circuit (311) judged that the main power supply (305) is at normal state.

Claims18

Dependent claims

A data write system for preventing a data store circuit from storing erroneous data therein so as to keep data stored therein while a data protect signal is generated, said data store circuit being supplied with a voltage by a power supply, comprising:

a power supply monitor coupled to the power supply for producing a first control signal selectively having first and second levels, the first level being produced when the voltage supplied from the power supply is greater than a predetermined level, the second level being produced when the voltage supplied from the power supply is less than or at the predetermined level;
a processor, connected to receive said voltage from the power supply, for generating a second control signal which has a data protect set mode and a data protect release mode and a third control signal which has a write permit mode and a write prohibit mode, in order to control said data store circuit;
a data protect setting and releasing circuit responsively coupled to said processor;
and
a data protect circuit responsively coupled to said data protect setting and releasing circuit and selectively generating the data protect signal which has a protect mode and a release mode;
said data protect setting and releasing circuit, when the second control signal has the data protect set mode and the third control signal has the write permit mode, setting said data protect circuit to generate the data protect signal having a protect mode only when the first control signal has the first level a predetermined first period of time after the third control signal has the write permit mode, and when the second control signal has the data protect release mode and the third control signal has the write permit mode, said data protect setting and releasing circuit further setting said data protect circuit to generate the data protect signal only when the first control signal has the first level the predetermined first period of time after the third control signal has the write permit mode, otherwise said protect setting and release circuit causing said data protect circuit to continue outputting the data protect signal.

3 more elements

A data write control system comprising:

a power supply for supplying a power supply voltage;
a power supply monitor coupled to the power supply for producing a voltage level detecting signal having a first level when the power supply voltage is greater than a predetermined level and a second level when the power supply voltage is less than or at the predetermined level;
a processor coupled for receiving the power supply voltage, for generating a data protect setting and releasing signal having a protect set mode and a protect release mode, a protect writing signal having a write mode and a write prohibit mode and a write control signal;
a data protect circuit for generating a data protect signal having either a third level or a fourth level, the data protect circuit changing the level of the data protect signal corresponding to the mode of the data protect setting and releasing signal when the protect writing signal has the write mode and the voltage level detecting signal has the first level after a first period of time from detecting the write mode of the protect writing signal, otherwise said data protect circuit maintaining the level of the data protect signal;
a write control circuit coupled to said data protect circuit and said processor for generating a write enable signal in response to the write control signal when the data protect signal has the third level, said write control circuit generating a write prohibit signal when the data protect signal has the fourth level;
and
a data store circuit coupled to the write control circuit for writing data when the write enable signal is received thereto.

4 more elements

A data write control system comprising:

a power supply for supplying a power supply voltage;
a power supply monitor coupled to the power supply for producing a voltage level detaching signal having a first level when the power supply voltage is greater than a predetermined level and a second level when the power supply voltage is less than or at the predetermined level;
a processor coupled for receiving the power supply voltage, for generating a data protect setting and releasing signal having a protect set mode and a protect release mode, a protect writing signal having a write mode and a write prohibit mode and a write control signal;
a data protect set and release discriminating circuit coupled to said processor and said power supply monitor for generating a discriminating signal having the protect mode when the data protect setting and releasing signal has a protect set mode and the protect writing signal has the write mode, said data protect set and release discriminating circuit generating the discriminating signal having a release mode when the data protect setting and releasing signal has the protect release mode and the protect writing signal has the write mode;
a data protect signal generating circuit coupled to said data protect set and release discriminating circuit for generating a data protect signal having either a third level or a fourth level, said data protect signal generating circuit generating the data protect signal having the third level where the voltage level detecting signal has the first level a predetermined time after the discriminating signal has the protect mode, said data protect signal generating circuit generating the data protect signal having the fourth level where the voltage level detecting signal has the first level the predetermined time after the discriminating signal has the release mode;
a write control circuit coupled to said data protect signal generating circuit and said processor for generating a write enable signal in response to the write control signal and the data protect signal having the third level, said write control circuit generating a write prohibit signal in response to the data protect signal having the fourth level;
and
a data store circuit coupled to the write control circuit for storing data in response to the write enable signal.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/012,618Filed 2 Feb 1993 · continuation
Priority: JP 63-32305521 Dec 1988
Granted: 20 Sep 1994
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 11/0754
Error or fault detection not based on redundancy: by exceeding limits
G06F 1/30
Power supply means, e.g. regulation thereof: means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
G06F 11/004
Error detection; Error correction; Monitoring: error avoidance
G11C 7/22
Arrangements for writing information into, or reading information out from, a digital store: read-write [R-W] timing or clocking circuits;…

Family

Serial566,453Parent of this continuation · filed 19 Aug 1990
US 5,349,669 AThis patent

From the US filing history. Foreign family members aren’t listed.

Timeline

Citations

Open elsewhere

Building an agent or pulling many patents? Use the API or MCP server instead of scraping pages. Get an API key