Reduced power line fluctuation/noise circuit by increasing impedance level when number of bus lines simultaneously change state exceeds the predetermined number

A single-chip microcomputer that stores data in an external memory and generates address signals to access the external memory, said microcomputer comprising:

• a central processing unit for generating said address signals;
• a plurality of address bus lines coupled to said central processing unit for transmitting said address signals;
• an output buffer circuit, coupled to said plurality of address bus lines, for driving said address signals to the external memory, said output buffer circuit introducing an impedance level on said plurality of address bus lines;
• a detector circuit, coupled to said plurality of address bus lines, for detecting how many of said address bus lines change state at a predetermined time;
• impedance varying means, coupled to said detector circuit and to said output buffer circuit, for increasing said impedance introduced by said output buffer circuit when the number of address bus lines that change state at said predetermined time is greater than a predetermined number so that through current of said output buffer circuit is reduced and power line fluctuation associated with said through current is reduced.