Hierarchical ordering of logical elements in the canonical mapping of net lists

In a computer automated design system for the design and logic synthesis of electronic circuits, the system comprising a cell library having a plurality of cell components for implementing an electronic circuit in a fabrication technology, each cell component having one or more nodes defined therein, a computer implemented method for hierarchically defining and ordering the cell components, comprising the steps of:

• converting each cell component into a canonical form cell component having a number of nodes;
• sequentially ordering all of said cell components based on the number of nodes contained in each cell component, with cell components having more nodes being higher in the hierarchy, to create an ordered array of cell components;
• for each cell component, hierarchically redefining the selected cell component in terms of cell components lower in the hierarchy than the selected cell component to create a plurality of hierarchical cell components in the ordered array of cell components;
• for each hierarchical cell component, comparing the hierarchical cell component with all other hierarchical cell components in the ordered array of cell components to determine whether any other hierarchical cell component is structurally identical to the hierarchical cell component;
• and
• eliminating from the ordered array of cell components any other hierarchical cell component which is structurally identical to the hierarchical cell component to ensure that each hierarchical, cell component is structurally distinct.