US 5,349,651 AGranted

System for translation of virtual to physical addresses by operating memory management processor for calculating location of physical address in memory concurrently with cache comparing virtual addresses for translation

AssigneeDigital Equipment Corporation

InventorsRicky C. Hetherington, David A. Webb, Jr., David B. Fite, John E. Murray, Tryggve Fossum, Dwight P. Manley

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Abstract

In the field of high speed computers it is common for a central processing unit to reference memory locations via a virtual addressing scheme, rather than by the actual physical memory addresses. In a multi-tasking environment, this virtual addressing scheme reduces the possibility of different programs accessing the same physical memory location. Thus, to maintain computer processing speed, a high speed translation buffer cache is employed to perform the necessary virtual-to-physical conversions for memory reference instructions. The translation buffer cache stores a number of previously translated virtual addresses and their corresponding physical addresses. A memory management processor is employed to update the translation buffer cache with the most recently accessed physical memory locations. The memory management processor consists of a state machine controlling hardware specifically designed for the purpose of updating the translation buffer cache. The memory management processor calculates an address of a location in the memory where the physical address is stored concurrently with the translation buffer cache comparing the virtual address with already stored virtual addresses. With this arrangement the memory management unit can immediately access memory to retrieve the physical address upon a "miss" by the translation buffer cache.

Claims16

Dependent claims

A memory access unit for controlling access to a memory by a data processing unit of a digital computer system, said data processing unit providing a plurality of virtual addresses to said memory access unit and said memory access unit providing a corresponding plurality of physical addresses to said memory, said memory having a plurality of memory locations, each of said memory locations storing one of the plurality of physical addresses, said memory access unit comprising:

a translation buffer including:
a) a translation buffer cache of previously converted virtual addresses and corresponding physical addresses,
b) means for comparing a current virtual address to the translation buffer cache of previously converted virtual addresses and delivering one of a miss and hit signal in response to respectively detecting an absence and presence of a match between the current virtual address and one of said previously converted virtual addresses, and
c) means responsive to receiving said hit signal for delivering to said memory the physical address from said translation buffer cache corresponding to the current virtual address;
and
a memory management processor for updating said translation buffer cache in response to receiving said miss signal, said memory management processor including:
a) means for calculating a memory address of one of said memory locations containing the physical address corresponding to said current virtual address,
b) means for retrieving the physical address corresponding to said current virtual address from the memory using the calculated memory address from the means for calculating, and
c) means for storing in said translation buffer cache the retrieved physical address in correspondence with said current virtual address;
wherein said translation buffer and said means for calculating are interconnected for receiving and operating concurrently upon a same virtual address from the data processing unit so that said means for calculating performs the calculation of the memory address of the memory location containing the physical address concurrently with the translation buffer performing the comparing of the current virtual address to the translation buffer cache of previously converted virtual addresses.

7 more elements

A memory management processor for controlling conversion of a plurality of virtual addresses to a corresponding plurality of physical addresses in a digital computer;

said digital computer having a data processing unit providing said virtual addresses, a memory receiving said physical addresses, said memory having a plurality of memory locations, each of said memory locations storing one of the plurality of physical addresses, and a translation buffer including a translation buffer cache of previously converted virtual addresses and corresponding physical addresses;
said translation buffer cache having means for comparing a current virtual address from said data processing unit to the translation buffer cache of previously converted virtual addresses, and delivering one of a miss and hit signal in response to respectively detecting an absence and presence of a match between the current virtual address and one of said previously converted virtual addresses, and means responsive to receiving said hit signal for delivering to said memory the physical address from said translation buffer cache corresponding to the current virtual address;
said memory management processor comprising, in combination:
means for calculating a memory address of one of said memory locations containing said physical address corresponding to said current virtual address, wherein said means for calculating is operative concurrently with said means for comparing said current virtual address to the translation buffer cache of previously converted virtual addresses;
means for retrieving said physical address corresponding to said current virtual address from the memory using the calculated memory address from the means for calculating in response to said miss signal;
means for storing in said translation buffer cache said retrieved physical address in correspondence with said current virtual address;
and
control means for operating said means for calculating concurrently with each of said virtual addresses being received by said translation buffer from said data processing unit and compared to the translation buffer cache of previously converted virtual addresses, and for controlling said means for retrieving and said means for storing in response to said miss signal, wherein said control means is a sequential state machine.

5 more elements

A method of controlling conversion of a plurality of virtual addresses to a corresponding plurality of physical addresses in a digital computer;

said digital computer having a data processing unit providing said virtual addresses, a memory receiving said physical addresses, said memory having a plurality of memory locations, each of said memory locations storing one of the plurality of physical addresses, and a translation buffer including a translation buffer cache of previously converted virtual addresses and corresponding physical addresses;
said translation buffer cache having means for comparing a current virtual address from said data processing unit to the translation buffer cache of previously converted virtual addresses, and delivering one of a miss and hit signal in response to respectively detecting an absence and presence of a match between the current virtual address and one of said translation buffer cache of previously converted virtual addresses, and means responsive to receiving said hit signal for delivering to said memory the physical address from said translation buffer cache corresponding to the current virtual address;
said method comprising the steps of:
concurrently with said translation buffer comparing the current virtual address from said data processing unit to the translation buffer cache of previously converted virtual addresses, operating an arithmetic unit to calculate a memory address of one of said memory locations containing said physical address corresponding to said current virtual address;
retrieving said physical address corresponding to said current virtual address from the memory using the calculated memory address from the arithmetic unit when said miss signal is delivered, and storing the retrieved physical address in said translation buffer cache;
and
retrieving the physical address corresponding to said current virtual address from the translation buffer cache when said hit signal is delivered.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/746,007Filed 9 Aug 1991 · continuation
Priority: 3 Feb 1989
Granted: 20 Sep 1994
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

G06F 12/0855
Multiple simultaneous or quasi-simultaneous cache accessing: overlapped cache accessing, e.g. pipeline
G06F 12/1045
Using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]: associated with a data cache
G06F
Computing and data processing

Family

Serial306,544Parent of this continuation · filed 3 Feb 1989
US 5,349,651 AThis patent

From the US filing history. Foreign family members aren’t listed.

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