Address translating apparatus for translating virtual address into real address without depending on processing by CPU

A data processing apparatus comprising:

• a memory cell array including a plurality of memory cells arranged in rows and columns;
• and
• address translating means for translating an externally applied virtual address signal into a real address signal for addressing said memory cell array, wherein said address translating means comprises
• offset data holding means for holding predetermined offset data for address translation,
• enabling means responsive to predetermined more significant bits of the virtual address signal and predetermined more significant bits of the offset data held in said offset data holding means for enabling access to said memory cell array, said enabling means having
• i) first coincidence detecting means for detecting coincidence of the more significant bits of the virtual address signal and the offset data held in said offset data holding means,
• ii) second coincidence detecting means for detecting coincidence between the more significant bits of the virtual address signal and data bits having a prescribed relationship with the more significant bits of the virtual address signal by addition of a prescribed value to the more significant bits of the virtual address, and
• real address signal generating means responsive to predetermined less significant bits of the virtual address signal and predetermined less significant bits of the offset data held in said offset data holding means for generating said real address signal, wherein said enabling means and real address signal generating means share a common address bus.

A data processing apparatus comprising:

• a memory cell array having first and second input/output ports and a plurality of memory cells arranged in rows and columns;
• first accessing means connected to the first input/output port of said memory cell array for accessing said memory cell array through the first input/output port;
• and
• second access means connected to the second input/output port of said memory cell array and responsive to an externally applied virtual address signal for accessing said memory cell array through the second input/output port, wherein said second access mean comprises
• offset data holding means for holding predetermined offset data for address translation,
• enabling means responsive to predetermined more significant bits of the virtual address signal and predetermined more significant bits of the offset data held in said offset data holding means for enabling access to said memory cell arrays, said enabling means having
• i) first coincidence detecting means for detecting coincidence of the more significant bits of the virtual address signal and the offset data held in said offset data holding means,
• ii) second coincidence detecting means for detecting coincidence between the more significant bits of the virtual address signal and data bits having a prescribed relationship with the more significant bits of the virtual address signal by addition of a prescribed value to the more significant bits of the virtual address, and
• real address signal generating means responsive to predetermined less significant bits of the virtual address signal and predetermined less significant bits of the offset data held in said offset data holding means for generating said real address signal, said enabling means and real address signal generating means sharing a common address bus and said memory cell array being responsive to the real address signal generated from said real address signal generating means to be addressed.