Programmable frequency divider circuit

A programmable frequency divider circuit, comprising:

• cascade-connected frequency dividing cells, a cell of rank i in the cascade performing an i.sup.th division, where i takes a value from 0 to (p-1), all cells being switchable between a normal divide-by-two mode and a programmed divide-by-three mode, a cell of arbitrary rank i comprising a first input (I.sub.i) for an input frequency signal (FI.sub.i) and a first output (O.sub.i) for an output frequency signal (FO.sub.i) to be applied to the first input (I.sub.i+1) of the next cell of rank (i+1), a second input (CI.sub.i) for an enable signal for the programmed mode, a third input (D.sub.i) for a programming signal, and a second output (CO.sub.i) for a gating signal, and means for generating said gating signal from the enable signal received on the second input (CI.sub.i) of the cell i, said gating signal being applied to the second input (CI.sub.i-1) of the cell (i-1) of lower rank as an enable signal, characterized in that the means for generating the gating signal are operative so that this signal is supplied from the instant at which the enable signal received by the relevant cell i returns to its inactive logic state, in that with the p cells which constitute a prescaler for the frequency divider circuit there are associated counting means for forming a first counting operation and a second counting operation for a first number and a second number, respectively, of periods of the output frequency of said prescaler, the second input (CI.sub.p-1) of the p.sup.th cell receiving an enable signal which is supplied by the counting means and which is derived from the completion of said first counting operation, the completion of said first and second counting operations constituting an output period of the divider circuit.