Timer access control apparatus
AssigneeUnisys Corporation
InventorsTheodore C. White, Jayesh V. Sheth, Kha Nguyen
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Abstract
An apparatus is disclosed that provides control of access to a module. In particular, the module should not be accessed while in a busy or unstable state. The module disclosed herein, by way of example, is a timer module. Access to the timer is controlled by the disclosed apparatus while the timer is changing state.
Claims8
An apparatus for controlling access to a timer circuit during periods of instability thereof, said apparatus comprising:
- a.) first terminal means disposed for receiving a count signal of said timer circuit;
- b.) second terminal means disposed for receiving a clock signal of said timer circuit;
- c.) third terminal means disposed for receiving a load-timer signal;
- d.) fourth terminal means disposed for receiving a read-timer signal;
- e.) means for generating a first modification of said count signal, including logic means for generating an inhibit signal in response to a positive transition of said load-timer signal and a positive transition of said count signal, and gating means for combining said inhibit signal and said count signal such that said first modified count signal is inactive during the presence of said inhibit signal;
- and,
- f.) means for generating a second modification of said count signal in response to said read-timer signal said clock signal and said first modified count signal, said second modification of said count signal being supplied for incrementing said timer circuit, whereby said timer circuit cannot be incremented during a read or load operation.
An apparatus for controlling access to a timer circuit during periods of instability thereof, said apparatus comprising:
- a.) first terminal means disposed for receiving a count signal of said timer circuit;
- b.) second terminal means disposed for receiving a clock signal of said timer circuit;
- c.) third terminal means disposed for receiving a load-timer signal;
- d.) fourth terminal means disposed for receiving a read-timer signal;
- e.) logic means for generating a logic signal in response to a positive transition of said load-timer signal and a positive transition of said count signal and gating means for combining said inhibit signal and said count signal such that said first modified count signal is inactive during the presence of said inhibit signal;
- f.) logic means for extending the period of said count signal one cycle in response to said read-timer signal, whereby said timer circuit cannot be incremented during a read or load operation, said logic means including a latch means for storing overlapping positive transitions of said count signal and said read-timer signal, said latch means being reset by the absence of said read-timer signal;
- and,
- g.) means for modifying said clock signal in response to said first modification of said count signal and said read-timer signal, including AND gating means responsive to said modified count signal and said read-timer signal and OR gating means responsive to said AND gating means and said clock signal, such that said clock signal is modified by deleting one transition thereof in response to said read-timer signal.
An apparatus in accordance with claim 8 wherein said means for modifying includes AND gating means responsive to said modified count signal and said read-timer signal, and OR gating means responsive to said AND gating means and said clock signal, such that said clock signal is modified by deleting one transition thereof in response to said read timer signal.
Dependencies are inferred from the claim text.