Digital serializer and time delay regulator
AssigneeAdvanced Micro Devices, Inc.
InventorsBin Guo, James J. Kubinec
Life of this patent
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Abstract
A self calibrated time delay circuit including a plurality of serially connected unit delay cells each having an output tap which is selectable, a registration means for simultaneously determining the status of each output node of each of the unit delay cells, combinatorial and sequential logic units for analyzing said registration means and sending error correction commands to an up/down controller, said up down controller providing a command code for controlling the delay of each said unit delay by selecting which tap is output from said unit delay cell.
Claims12
A digitally regulated time delay circuit comprising a plurality of delay units, each said delay unit calibrated to exhibit a time delay T, where T.ltoreq.Tb, and Tb is a bit period, each delay unit having an input terminal and an output terminal, said delay units being connected in series;
- means to launch a pulse having a width less than a bit period into said input terminal of one of said plurality of delay units;
- a phase detector, said phase detector being connected to the output of the last of said plurality of delay units, said phase detector having an output, said phase detector comprising,
- (a) a delay line having a plurality of taps,
- (b) a registration means, said registration means coupled to the output of a plurality of said delay units and to each of said phase detector delay line taps, said registration means for determining simultaneously on-the-fly the status of each node to which it is connected and for providing an output indicative thereof, and
- (c) combinatorial and sequential logic means coupled to said registration means output, said combinatorial and sequential logic means providing an output indicative of said delay status, said combinatorial and sequential logic means output being said phase detector output;
- an up/down controller, said up/down controller being connected to and responsive to said phase detector output, said up/down controller providing an output which is a digital command code for control of said delay units;
- and
- wherein each said plurality of delay units is connected to and responsive to said up/down controller digital command code.
The delay circuit of step 2 wherein said coarse step unit includes a MUX, said MUX having one input for receiving one output from each of said delay units, said MUX further having one output.
The delay circuit of step 3 wherein one of said MUX inputs is made available at said MUX output and wherein the selection available at said MUX output is responsive to and determined by said digital command code.
A digital data serializer for high data rate transmission having a bit frequency equal to 1/Tb comprising a first plural stage register for latching a multibit word to be serialized, each said register stage having an output;
- a gating network, said gating network including a plurality of switches, each said switch including an input, output and control terminal, the output terminal of all the said switches coupled to a node and the input terminal of each said switch connected to a different one of said register stage outputs;
- a digitally regulated time delay circuit, comprising a plurality of nominal 1/2 Tb delay units connected in series from their inputs to their outputs, and
- each control terminal of said gating network switches being connected to a different said input of one of said 1/2 Tb units.
An all digital method for regulating a delay line which is transmitting a serial pulse train having a bit frequency equal to 1/Tb comprising
- launching a pulse having a pulse width equal to 1/2 Tb into said delay line, said delay line including a plurality of serially connected delay units having a nominal delay equal to 1/2 Tb;
- determining the position of any instant of said pulse in said delay line;
- adjusting said delay of each said 1/2 Tb delay units responsive to the said position of said pulse in said delay line.
Dependencies are inferred from the claim text.