Digital data detecting and synchronizing circuit

A digital data detecting circuit for forming a receiving clock signal synchronized with every bit of digital data and detecting contents of the digital data, said digital data detecting circuit comprising:

• a synchronuous signal generating counter, responsive to a reference clock signal, for generating the receiving clock signal sychronized with every bit of digital data;
• a data-changing point detecting circuit for detecting a changing point of the digital data at which a value indicative of the digital data is changed from value 1 to value 0, or value 0 to value 1;
• a masking pattern control circuit, responsive to a signal from the synchronous signal generating counter, for determining a masking bit to be masked in accordance with a shift amount of the timing of the changing point;
• and
• a masking circuit, responsive to the masking pattern control circuit, for masking a bit of an output of the synchronous signal generating counter when the changing point is detected by the data-changing point detecting circuit;
• and
• a reset control circuit for controlling the timing of a reset operation of said synchronous signal generating counter based on an output of the masking circuit.

A digital data detecting circuit for forming a receiving clock signal synchronized with every bit of digital data and detecting contents of the digital data, said digital data detecting circuit comprising:

• a synchronous signal generating counter, responsive to a reference clock signal, for generating a synchronous signal;
• a changing point detecting circuit for detecting a changing point of the digital data at which a value indicative of the digital data is changed from value 1 to value 0, or value 0 to value 1, said changing point detecting circuit using a selectable pulse width for noise judgment and neglecting a noise having a pulse width equal to or less than said pulse width for noise judgment;
• an synchronous frequency detecting circuit, responsive to an output of the changing point detecting circuit, for detecting asynchronizations occurring in a constant period and outputting a signal in accordance with the frequency of asynchronizations;
• and
• a reset control circuit for controlling the timing of a reset operation of said synchronous signal generating counter in accordance with said output of the changing point detecting circuit and the signal output from said asynchronous frequency detecting circuit.

A method for forming a receiving clock signal synchronized with every bit of digital data and detecting contents of the digital data, said method comprising the steps of:

• detecting a changing point of the digital data at which a value indicative of the digital data is changed from value 1 to value 0, or value 0 to value 1;
• detecting asychronizations in response to the detected changing point by judging whether or not said changing point occurs at the timing of a reference clock signal;
• counting the number of detected asynchronizations;
• and
• controlling the timing of a reset operation of a synchronous signal generating counter generating the receiving clock signal sychronized with every bit of digital data in accordance with the detected changing point and the detected number of asynchronizations.