Memory device with pulse circuit for timing data output, and method for outputting data

A memory device comprising:

• a memory array;
• an output buffer operatively coupled to the memory array, the output buffer temporarily storing data that is retrieved from the memory array during a read cycle, the output buffer holding the data until it is replaced by subsequently retrieved data;
• and
• a pulse circuit operatively coupled to the memory array and the output buffer, the pulse circuit outputting a pulse signal as soon as data is valid which causes the output buffer to store the retrieved data, the pulse circuit being configured to output a pulse signal of fixed duration.

A memory device comprising:

• a memory array;
• an output buffer operatively coupled to the memory array, the output buffer temporarily storing data that is retrieved from the memory array during a read cycle, the output buffer holding the data until it is replaced by subsequently retrieved data;
• and
• a pulse circuit operatively coupled to the memory array and the output buffer, the pulse circuit outputting a pulse signal as soon as data is valid which causes the output buffer to store the retrieved data, the pulse circuit being configured to output a pulse signal of variable duration.

A memory device comprising:

• a memory array for storing data;
• a read/write system for providing row and column address signals for accessing the data stored in the memory array during a read cycle;
• a data present circuit for providing a data present signal when the data is retrieved from the memory array;
• a sliding pulse circuit operatively coupled to the read/write system and the data present circuit, the sliding pulse circuit providing a data valid signal upon receipt of both the data present signal and the column address signal;
• a row address valid circuit operatively coupled to the read/write system and the sliding pulse circuit, the row address valid circuit generating a pulse signal upon receipt of the row address signal and the data valid signal;
• and
• an output buffer, operatively coupled to the memory array, for temporarily storing the retrieved data upon receipt of the pulse signal from the row address valid circuit.

A method for outputting data from a memory device, the method comprising the following steps:

• providing a memory array having data stored therein;
• addressing the memory array to retrieve the data;
• reading the data from the memory array;
• generating a pulse signal when both (1) the memory array is addressed and (2) the data is read from the memory array;
• and
• transferring the data from the memory array to the output buffer in response to the pulse signal.

A method for outputting data from a memory device, the method comprising the following steps:

• providing a memory array having first and second data stored therein;
• addressing a first memory location containing the first data;
• reading the first data from the memory array;
• generating a first pulse signal when the first memory location is addressed and the first data is read from the memory array;
• transferring the first data from the memory array to an output buffer in response to the first pulse signal;
• temporarily holding the first data in the output buffer;
• addressing a second memory location containing the second data;
• reading the second data from the memory array;
• generating a second pulse signal when the second memory location is addressed and the second data is read from the memory array;
• and
• transferring the second data from the memory array to the output buffer to replace the first data in response to the second pulse signal.