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US 5,349,565 AGranted
SRAM with transparent address latch and unlatched chip enable
AssigneeMOS Electronics Corporation
InventorsSheau-Dong Wu, Iu-Lin Lih
Life of this patent
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Abstract
A latch ram including on a single chip a memory array, an address latch and associated row and column decoders for addressing particular locations within the memory array, data I/O and associated column I/O circuitry for inputting data to and outputting data from the memory array, and microprocessor-controlled logic for controlling the input and output of such data. The device is packaged in a 28-pin DIP or SO package.
Claims12
A single chip address latched SRAM device comprising:
- a memory array organized to store data in a word format with each word containing a predetermined number of data bits;
- address latch means having a plurality of input address lines and a plurality of output lines and operative to latch row address and column address inputs addressing particular locations in said memory array, and an address latch enable (ALE) input line, said address latch means being functionally transparent when an ALE input signal of a first logic state is applied to said ALE input line, said address latch means being operative to latch said output lines when an ALE input signal of a second logic state is applied to said ALE input line;
- data input/output means having a plurality of data input/output lines and a control input, said data input/output means being operative to selectively couple said plurality of data input/output lines to said memory array, and responsive to a control signal applied to said control input to determine when data is to be input thereto or output therefrom;
- and
- control logic means having at least three unlatched chip input lines for respectively receiving an output enable signal (G), a chip enable signal (E) and a write enable signal (W), said control logic means being directly responsive to the three enable signals G, E and W, and operative to develop said control signal for controlling said data I/O means such that when G is of one state and W is of one state, data from said memory array will be output to said input/output lines, and when W is of a second state and G is of a second state, data present on said input/output lines will be written into an addressed memory location, and wherein when E is of a first logic state, said memory array is selected, and when E is of a second logic state, said memory array is deselected.
2 more elements
In a microcontroller including a microprocessor and one or more memory devices for storing processing data, an improved random access memory means embodied in one or more single chip integrated circuit devices each comprising:
- a memory array organized to store data in a word format with each word containing a predetermined number of data bits;
- address latch means having a plurality of input address lines and a plurality of output lines and operative to latch row address and column address inputs addressing particular locations in said memory array, and an address latch enable (ALE) input line, said address latch means being functionally transparent when an ALE input signal of a first logic state is applied to said ALE input line, said address latch means being operative to latch said output lines when an ALE input signal of a second logic state is applied to said ALE input line;
- data input/output means having a plurality of data input/output lines and a control input, said data input/output means being operative to selectively couple said plurality of data input/output lines to said memory array, and responsive to a control signal applied to said control input to determine when data is to be input thereto or output therefrom;
- and
- control logic means having at least three unlatched chip input lines for respectively receiving an output enable signal (G), a chip enable signal (E) and a write enable signal (W), said control logic means being directly responsive to the three enable signals G, E and W, and operative to develop said control signal for controlling said data I/O means such that when G is of one state and W is of one state, data from said memory array will be output to said input/output lines, and when W is of a second state and G is of a second state, data present on said input/output lines will be written into an addressed memory location, and wherein when E is of a first logic state, said memory array is selected, and when E is of a second logic state, said memory array is deselected.
2 more elements
Dependencies are inferred from the claim text.