Dynamic random access memory device suitable for shortening time required for testing self-refresh function

A dynamic random access memory device having self-refresh function, comprising:

• a memory cell array having a plurality of memory cells arranged in rows and columns;
• refresh address generating means responsive to an applied clock signal for generating a refresh address signal;
• designating means responsive to the refresh address signal for designating a memory cell to be refreshed in said memory cell array;
• first clock signal generating means for generating a first clock signal having a first frequency defining a refresh cycle in a normal self-refresh mode;
• means for receiving an externally applied second clock signal having a second frequency higher than said first frequency;
• and
• selective supply means responsive to an externally applied test mode signal for selectively supplying one of said first and second clock signals to said refresh address generating means.

A dynamic random access memory device having self-refresh function, comprising:

• a memory cell array having a plurality of memory cells arranged in rows and columns;
• refresh counter means for generating a refresh address signal by counting applied clock signals;
• address decoder means for designating a memory cell to be refreshed in said memory cell array by decoding the refresh address signal;
• internal clock signal generating means for generating and applying to said refresh counter means internal clock signals having a first frequency defining a refresh cycle in a normal self-refresh mode;
• and
• frequency selecting means responsive to an externally applied test mode signal for selectively applying to said refresh counter means said internal clock signals or external clock signals from an externally applied clock signal having a frequency higher than said internal clock signals.

A dynamic random access memory device selectively carrying out an externally requested refresh operation and a self-refresh operation, comprising:

• a memory cell array having a plurality of memory cells arranged in rows and columns;
• first refresh address generating means responsive to an externally applied refresh request signal for generating a refresh address signal;
• second refresh address generating means for automatically generating a refresh address signal when said refresh address request signal is not applied;
• and
• designating means responsive to the refresh address signals applied from said first and second refresh address generating means for designating a memory cell to be refreshed in said memory cell array;
• wherein said second refresh address generating means includes:
• first clock signal generating means for generating first clock signals having a first frequency defining a refresh cycle in a normal self-refresh mode,
• second clock signal generating means for generating second clock signals having a second frequency higher than said first frequency,
• refresh counter means for counting either of said first and second clock signals applied from said first and second clock signal generating means to generate a refresh address signal, and
• selective supply means responsive to an externally applied test mode signal for selectively applying one of said first and second clock signals to said refresh counter means.