Semiconductor memory device with improved bit line precharged circuits

A semiconductor memory device having a number of memory cells each sharing a pair of bit lines, each bit line pair together with corresponding memory cells forming a memory cell array, said semiconductor memory device comprising:

• first bit line precharge means coupled to a first position along a bit line pair for precharging the bit lines of said bit line pair;
• and
• second bit line precharge means coupled at a second position along said bit line pair for also precharging said bit lines of said bit line pair, said first and second positions substantially corresponding to respective opposite ends of said bit line pair to reduce a precharge time associated with said bit line pair and defining a positional distance within which there is also included all memory cells associated with said bit line pair.

A semiconductor memory device having a number of memory cells each sharing a pair of bit lines, each bit line pair together with corresponding memory cells forming a memory cell array, said semiconductor memory device comprising:

• first bit line precharge means coupled to a first position along a bit line pair for precharging the bit lines of said bit line pair;
• and
• second bit line precharge means coupled at a second position along said bit line pair for also precharging said bit lines of said bit line pair, said first and second positions substantially corresponding to respective opposite ends of said bit line pair to reduce a precharge time associated with said bit line pair so that the precharge time is substantially identical with respect to any selected memory cell associated with said bit line pair.