Sector-based redundancy architecture

A semiconductor integrated circuitry memory device having array means formed of a plurality of sectors each formed of an array of flash EEPROM cells and redundancy circuit means for repairing defective columns of memory cells in the plurality of sectors on a sector-by-sector basis, said redundant circuit means comprising in combination:

• a plurality of sector-based redundancy blocks (12-26) each having redundant columns of memory cells extending through the plurality of sectors;
• sector selection means (Q1,Q2) for dividing said redundant columns into different segments each residing in at least one of said plurality of sectors and for isolating the different segments so as to allow independent use from other segments in the same redundant columns in repairing the defective columns in corresponding ones of said plurality of sectors;
• addressable storage means (314) for storing sector-based redundancy column addresses each defining a column address containing the defective column of memory cells in the plurality of sectors in association with one of the different redundant column segments to be used in repairing the defective column;
• said addressable storage means including means responsive to sector address signals and address input signals for programming said redundant column addresses;
• said addressable storage means including means (316) for reading said stored redundancy column addresses in relation to said plurality of sector-based redundancy blocks and for comparing said address input signals with said redundancy column address which is being read to generate a redundancy signal and a disable signal when there is a match;
• means (318a,318b) responsive to said redundancy signal for enabling said redundant block to be used to repair said defective columns;
• means (318c) responsive to said disable signal for disabling a Y-decoder to the defective columns;
• said addressable storage means (314a) including a first addressable storage circuit for storing said redundancy column addresses corresponding to a first redundant element in each of said plurality of sector-based redundancy blocks and a second addressable storage circuit (314b) for storing said redundancy column addresses corresponding to a second redundant element in each of said plurality of sector-based redundancy blocks;
• each of said first and second addressable storage circuit being formed of a plurality of quad address circuits (315a-315g);
• the number of said quad address circuits being independent upon the number of columns in said plurality of sectors;
• each of said quad address circuits consisting of a plurality of single address bit storage circuits (319a-319d) whose outputs are arrayed so as to share a common read path, each of said quad address circuits being used to store a bit address of said redundancy column address associated with each of said plurality of sector-based redundancy blocks;
• the number of said single address bit storage circuits being dependent upon the number of said plurality of sector-based redundancy blocks;
• and
• each of said plurality of single address bit storage circuits having a single address bit storage cell formed of a program transistor device (DP) for storing one of said bit addresses associated with one of said plurality of sector-based redundancy blocks and a read transistor device (DR) responsive to said sector address signals for reading said stored redundancy column address.