US 5,349,555 A · Redundancy circuit

Abstract

In order to obtain a redundancy circuit which can freely arrange its fuse in a required position with disciplined accessibility after employment, a combination circuit (50) receives outputs (QA0 to QA7) obtained by decoding a column address (AXM) by a column line decoder (2), signals (QB0 to QB7) indicating a faulty line, signals (L0 to L7) generated from the signals (QB0 to QB7) and an inverted signal (ENB*), to generate signals (YS0 to YS8) for controlling selecting switches for specifying column lines. If a K-th column line is faulty, a column line selecting switch for selecting the K-th column line is forcibly turned off and an (N+1)-th column line is allocated with respect to specification of an N-th column line (N.gtoreq.K). Thus, fuse positions of redundancy circuits can be standarlized between products so that the products can be easily mass-produced and supplied at a low cost even if the redundancy circuits are contained in small quantities of various ASICs.

Claims17

Dependent claims

A redundancy circuit comprising:

(a) storage means having (M+N) storage columns including M specific redundant columns, each said storage column being substantially formed by a plurality of storage units;
(b) faulty column specifying means for outputting a faulty column signal indicating J faulty columns being storage columns having faulty said storage units;
(c) column signal specifying means for outputting a column signal indicating specific one of said storage columns and a match signal indicating match/mismatch of said specific one of storage columns and said faulty columns;
(d) a combination circuit receiving said column signal, said faulty column signal and said match signal for specifying one of .said specific redundant columns in correspondence to said specific one of storage columns when said specific one of storage columns is a faulty column;
and
(e) an enable circuit for generating an enable signal for controlling the operation of said combination circuit,
where M and N represent positive integers and J (.ltoreq.M) represents a non-negative integer.

4 more elements

Dependencies are inferred from the claim text.

Redundancy circuit

Life of this patent

Redundancy circuit

Life of this patent

Abstract

Claims17