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US 5,349,553 AGranted
Nonvolatile semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsSeiji Yamada, Masamitsu Oshikiri
Life of this patent
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Abstract
A nonvolatile semiconductor memory device comprises a memory cell array including memory cell transistors having a lamination gate structure are arranged in a matrix manner at the position where a word line and a bit line cross each other. A lower voltage than a threshold voltage is applied to the word line selected at the time of a reading mode in a state that no electrical charge is stored in the floating gate.
Claims5
A nonvolatile semiconductor memory device comprising:
- a memory cell array including a plurality of memory cell transistors arranged in a row and column matrix, wherein said memory cell transistors comprise a floating gate and a control gate having a lamination gate structure;
- a word line group having a plurality of word lines, wherein each word line corresponds to a row of said memory cell array and is connected in common to said memory cell transistors arranged in the corresponding row of said memory cell array;
- a bit line group having a plurality of bit lines, wherein each bit line corresponds to a column of said memory cell array and is connected in common to said memory cell transistors in the corresponding column of said memory cell array;
- row decoder means, connected to each word line, for selectively driving an arbitrary word line of said word line group, wherein said row decoder means when in a read mode applies a voltage to the arbitrary word line that is lower than a threshold voltage of said memory cell transistors in a state in which said floating gate stores no electrical charge;
- and
- column decoder means, connected to each bit line, for selectively driving an arbitrary bit line of said bit line group when in the read mode.
3 more elements
Dependencies are inferred from the claim text.