Non-integral delay circuit

Abstract

A non-integral delay circuit for delaying a digital signal by a selectable fraction (.delta.) of a sampling period of the digital signal includes a first differentiator (S3) to obtain a first differential signal (F1) having a first phase characteristic with respect to the digital signal, a second differentiator (D) to obtain a second differential signal (F2) having a second phase characteristic with respect to the digital signal, the first and second phase characteristics differing from each other, a mixer (MIX) for combining the first (F1) and second (F2) differential signals in dependence on the selectable fraction (.delta.) to obtain a phase-adjusted correction signal, and an adder (A9) which adds a product (M3) of the selectable fraction (.delta.) and the phase-adjusted correction signal to the digital signal, to obtain the digital signal delayed by the selectable fraction (.delta.) of the sampling period of the digital signal.

Dependencies are inferred from the claim text.