Image interpolation circuit

An image interpolation circuit comprising:

• first through fourth latches storing X abscissa and Y ordinate values of two coordinate points input by an external input unit;
• first and second comparators connected to said for comparing sizes between input X1 and X2 abscissa points and between input Y1 and Y2 ordinate points;
• first and second subtracters connected to said first and second comparators, respectively, for obtaining absolute values of the differences between input X1 and X2 abscissa points and between input Y1 and Y2 ordinate points;
• first and second load adders connected to said first and second subtracters, respectively, for adding absolute values of the X1 and X2 abscissa points and of said Y1 and Y2 ordinate points to the loaded values, after loading absolute values of said X1 and X2 abscissa points and of said Y1 and Y2 ordinate points obtained from said first and second subtracters;
• an absolute value comparator connected to said first and second load adders, for comparing outputs of said first and second load adders;
• first and second programmable up and down counters connected to said second and fourth latches and said first and second comparators, respectively, for outputting an interpolation signal by up or down counting said first X axis abscissa value or said Y axis ordinate value having a larger absolute value as a result of the comparison of said absolute value comparator;
• first and second interpolation comparators connected to said first and second programmable up and down counters, for disabling said first and second programmable up and down counters by comparing outputs of said first and second programmable up and down counters with the second X axis input value and Y axis input value;
• control signal generating means connected to said absolute value comparator, for outputting count enable signals of said first and second programmable up and down counters by using the output of said absolute value comparator;
• selection signal generating means connected to said control signal generating means, for controlling loads for adding said first and second load adders by using an output signal of said control signal generating means;
• and
• a clock generator connected to said control signal generating means, for generating a clock to control an operation of said first and second load adders by assembling an output signal of said control signal generating means with an outside clock signal.