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US 5,349,352 AGranted
Analog-to-digital converter having high AC line noise rejection and insensitive to AC line frequency variations
AssigneeHarris Corporation
InventorFarid Saleh
Life of this patent
Estimating the term…
Abstract
Analog-to-digital (AID) converters with power line frequency noise rejection by synchronization of the converter clock with the power line frequency through a phase locked loop. Both sigma delta and integrating A/D converters may use the synchronized clock to precisely reject power line frequency noise.
Claims16
An analog-to-digital converter, comprising:
- (a) a sigma-delta modulator;
- (b) a digital filter coupled to said modulator;
- (c) a clock generator providing clock signals at a clock frequency to said modulator and to said filter, wherein said clock frequency is a fixed multiple of a variable power line frequency;
- and
- (d) wherein said digital filter is a comb filter with a notch at a fixed fraction of said clock frequency which equals said power line frequency.
2 more elements
An analog-to-digital converter, comprising:
- (a) a sigma-delta modulator;
- (b) a digital filter coupled to said modulator;
- (c) a clock generator providing clock signals at a clock frequency f.sub.CLK to said modulator and to said filter, said clock generator includes a phase-locked-loop coupled to an AC power line at a frequency f.sub.LINE which may vary but fixes f.sub.CLK =Kf.sub.LINE for a positive integer K;
- and
- (d) wherein said digital filter has a stopband at f.sub.LINE.
2 more elements
An integrating analog-to-digital converter (dual/multislope), comprising:
- (a) a signal integrator driven by a clock generator;
- (b) said clock generator providing clock signals at a clock frequency f.sub.CLK coupled to said signal integrator, said clock generator including a phase-locked-loop coupled to an AC power line operating at frequency f.sub.LINE which may vary but fixes f.sub.CLK =Kf.sub.LINE for a positive integer K;
- (c) wherein the duration of an integrating interval by said signal integrator is an integer multiple of 1/f.sub.LINE ;
- and
- (d) wherein the clock frequency of the analog-to-digital converter is continuously adapted to the AC power line frequency.
2 more elements
An analog-to-digital converter comprising:
- (a) a sigma-delta modulator;
- (b) a digital filter coupled to said modulator;
- (c) a clock generator providing clock signals at a clock frequency to said modulator and to said filter, wherein said clock frequency is a fixed multiple of a variable power line frequency;
- and
- wherein said digital filter includes:
- (i) a low pass filter with a cutoff frequency higher than said lower line frequency;
- and
- (ii) an averaging filter coupled to an output of said low pass filter, said averaging filter averaging a fixed integral number of samples for a period of said power line frequency.
5 more elements
An analog-to-digital converter comprising:
- (a) a sigma-delta modulator;
- (b) a digital filter coupled to said modulator;
- (c) a clock generator providing clock signals at a clock frequency f.sub.CLK to said modulator and to said filter, said clock generator includes a phase-locked-loop coupled to an AC power line at a frequency f.sub.LINE which may vary but fixes f.sub.CLK =Kf.sub.LINE for a positive integer K;
- and
- (d) wherein said digital filter is an Nth order comb filter with a notch at f.sub.LINE.
2 more elements
Dependencies are inferred from the claim text.