US 5,349,350 A · Run length limited encoding/decoding system for low power disk drives

Abstract

The run length limited encoding/decoding system of this invention includes a clock swap logic circuit, a read reference clock multiplexer circuit, a write clock skip logic circuit, an encoder start logic circuit, an encoder circuit, a read clock skip logic circuit, a decoder start logic circuit, a decoder circuit, an input data buffer and a three-state output data buffer. The encoder circuit includes a deserializer for receiving serial data from a disk controller and blocking the data into m bit words. Each m bit data word is supplied directly to an encoding combinatorial logic circuit which in turn generates an n bit code word. The n bit code word is loaded in a serializer and serially transmitted out of the serializer. The decoder circuit includes a deserializer/serializer and a decoding combinatorial logic circuit. The deserializer/serializer receives a serial stream of encoded data and converts the data into n bit code words. Each n bit code word is loaded directly into the decoding combinatorial logic circuit which in turn generates an m bit data word. The m bit data word is loaded into the deserializer/serializer so that as the next n bit code word is serially loaded in the deserializer/serializer, the m bit data worded is serially moved out of the deserializer/serializer.

Claims34

Dependent claims

A run length limited encoding/decoding system comprising:

deserializer circuit means operatively coupled to a serial data stream and having a plurality of parallel output terminals and a clock terminal wherein said deserializer circuit means blocks said serial data stream into m bit data words;
encoding logic circuit means connected to said plurality of parallel output terminals of said deserializer means and having a plurality of parallel output terminals wherein said encoding logic circuit means converts an m bit data word into an n bit code word;
and
an n bit serializer circuit means connected to said plurality of parallel output terminals of said encoding logic circuit means and having a clock terminal and a serial output terminal wherein said serializer circuit means converts said n bit code word to a serial data stream that is supplied to said serial output terminal.

1 more element

A circuit comprising a run length limited encoder portion, said encoder portion comprising:

first input means for receiving data bit information;
first means for shifting, said first means for shifting having a serial input means for receiving data bit information from said first input means;
means for controlling said first means for shifting, said means for controlling causing said first means for shifting to shift during two consecutive pulses of a write clock and not to shift during a third pulse of said write clock following said two consecutive pulses wherein said means for controlling blanks every third pulse of a clock signal;
output means for outputting code bit information according to a run length limited encoding scheme performed on data bit information received by said first input means, said code bit information being serially output by the output means at an output code bit rate;
and
second input means for receiving a write clock, said write clock clocking at the output code bit rate, all other signals in the encoder portion clocking at rates no faster than said rate of said write clock.

3 more elements

An integrated circuit comprising:

decoder start logic circuit means having a code clock input line, a preamble detect input line, a decoder start output line, and another output line;
read clock skip logic circuit means having an input line connected to said decoder start output lie, a code clock input line, a decoder load output line and a decoder shift output line;
and
decoder circuit means having a first input line connected to said decoder load output line, a second input line connected to said decoder shift output line, a third input line connected to said decoder start output line, a fourth input line connected to said another output line of said decoder start logic circuit means, a code data input line, a code clock input line and a read data output line.

1 more element

Dependencies are inferred from the claim text.

Run length limited encoding/decoding system for low power disk drives

Life of this patent

Run length limited encoding/decoding system for low power disk drives

Life of this patent

Abstract

Claims34