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AssigneeAlcatel Network Systems, Inc.
InventorsKlaus-Hartwig Rieder, Gunter Horsch, William E. Powell
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The circuit arrangement of the invention presents an oscillator, whose frequency can be linearly varied within a wide control range, without affecting the oscillator's stability. The frequency of a fixed frequency generator (1) is divided to the desired frequency by a frequency divider (2), whose divider ratio can be varied in very small steps, and the resulting jitter is filtered out by a very simple phase control circuit (3). Improved short-term stability and holdover performance are also achieved. The oscillator can be universally used as clock generator in all digital circuit arrangements.
A controllable oscillator, comprising a fixed frequency generator (1) connected to a frequency divider (2) with an adjustable divider ratio, wherein the output of the frequency divider (2) is connected to the input of a phase detector of an analog phase control circuit (3), wherein the frequency divider (2) comprises a register, whose output is connected to a first input of an adder, wherein a second input of the adder is connected to a microprocessor (OBC), and wherein an output of the adder is connected to a nominal frequency input of the phase detector of the analog phase control circuit (3).
A controllable oscillator, comprising a fixed frequency generator (1) connected to a frequency divider (2) with a dynamically controlled divider ratio, wherein the output of the frequency divider (2) is connected to the input of a phase detector of an analog phase control circuit (3), wherein the fixed frequency generator (1) is connected to the nominal frequency input of the phase detector through a frequency divider, wherein the input of the frequency divider (2) with a dynamically controlled divider ratio is connected to the output of the analog phase control circuit (3), and wherein the output of the frequency divider (2) with a dynamically controlled divider ratio is connected to the comparison frequency input of the phase detector in analog phase control circuit (3), wherein the frequency divider with a dynamically controlled divider ratio comprises an adder having one input connected to a register and another input to a signal processor, the adder having one output connected to an input of the register and a carry output of the adder used as the output of the frequency divider (2) and wherein the fixed frequency generator (1) is connected to a clock input of the register.
Dependencies are inferred from the claim text.