Sense amplifier input stage for single array memory
AssigneeHoneywell Inc.
InventorLavon K. Cooper
Life of this patent
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Abstract
Sense amplifier input stage for reading the output of a single array memory having an "unknown" output, a reference "one" output and a reference "zero" output. A first differential amplifier compares the "unknown" output to the reference "one" output, and a second differential amplifier compares the unknown output to a reference zero output. The first and second differential amplifier share the same load Y resistors. Voltage offsets arising in the memory and in the sense amplifier input stage are compensated before the comparisons are made. When the unknown is a one the output has a first polarity and when the unknown is a zero, the output has an opposite polarity.
Claims14
A sense amplifier input stage for single array memory, comprising:
- a first reference line coupled to a first reference signal representing a first memory state;
- a second reference line coupled to a second reference signal representing a second memory state;
- an unknown line coupled to an unknown signal representing an unknown memory state;
- a first differential amplifier having a first input coupled to said unknown line and a second input coupled to said first reference line, said first differential amplifier having a first output connected to said first load and a second output load connected to said second load;
- a second differential amplifier having a first input coupled to said unknown line and a second input coupled to said second reference line, said second differential amplifier having a first output lead connected to said first load and a second output lead connected to said second load;
- means for compensating for offset voltages existing within said single array memory and within said sense amplifier input stage;
- and
- means for momentarily introducing said unknown signal, said first reference signal, and said second reference signal simultaneously to cause an output of said input stage between said first load and said second load, said output having a first polarity when said unknown signal corresponds to said first reference signal and a second polarity when said unknown signal corresponds to said second reference signal.
A sense amplifier input stage for single array memory, comprising:
- an unknown line coupled to an unknown signal representing an unknown memory state;
- a first reference line coupled to a first reference signal representing a first known memory state;
- a second reference line coupled to a second reference signal representing a second known memory state;
- a first differential amplifier having a first input coupled to said unknown line and a second input coupled to said first reference line, said first differential amplifier having a first output lead connected to a first load and a second output lead connected to a second load;
- a second differential amplifier having a first input coupled to said unknown line and a second input coupled to said second reference line, said second differential amplifier having a first output lead connected to said first load and a second output lead connected to said second load;
- a third differential amplifier having a first input coupled to said first reference line and a second input coupled to said second reference line, said third differential amplifier having a first output lead connected to a third load and a second output lead connected to said third load;
- means for compensating for offset voltages existing within said single array memory and within said first, second, and third differential amplifiers;
- and
- means for momentarily introducing said unknown signal, said first reference signal and said second reference signal simultaneously to cause an output of said input stage between said first load and said second load, said output having a first polarity when said unknown signal corresponds to said first reference signal and a second polarity when said unknown signal corresponds to said second reference signal.
Dependencies are inferred from the claim text.