Logic translator interfacing between five-volt TTL/CMOS and three-volt CML

A logic translator suited for low voltage operation comprising:

• a first input terminal for receiving an input signal having an input signal voltage relative to a common reference terminal;
• voltage reference means for providing a reference voltage relative to the common reference terminal at a first reference terminal;
• first and second transistors connected in a common emitter configuration between a supply terminal and the common reference terminal;
• a voltage clamp transistor connected between the base of the second transistor and the common reference terminal with the base of the voltage clamp transistor connected to the first reference terminal;
• voltage drop means connected between the base of the first transistor and the base of the voltage clamp transistor for providing a voltage drop thereacross so that a voltage between the bases of the first and second transistors has a magnitude that is less than a magnitude of a voltage equivalent to one diode drop;
• switching means connected to the second transistor for providing current thereto based on the input signal voltage;
• and
• at least one output terminal for providing an output voltage based on one of the first and second transistor currents.

A logic translator suited for low supply voltage operation, the logic translator being capable of receiving a TTL compatible signal and providing a current mode logic signal based thereon, the logic translator comprising:

• a first input terminal for receiving a TTL compatible signal having a TTL compatible signal voltage relative to a common reference terminal;
• voltage reference means for providing a reference voltage relative to the common reference terminal at a first reference voltage terminal with the reference voltage having a magnitude that is less than a voltage equivalent to three times a magnitude of one diode drop;
• current switch means for selectively allowing current flow in a first and second collector circuit, the current switch means comprising:
• first and second NPN transistors having emitters connected together with each NPN transistor having a base and with the first NPN transistor having a collector connected to the first collector circuit and the second NPN transistor having a collector connected to the second collector circuit and with the second NPN transistor having a base connected to the reference voltage means;
• a third transistor having first and second controlled terminals and a control terminal with the first and second controlled terminals connected between the common reference terminal and the emitters of each of the first and second NPN transistors;
• and
• control means for providing a control signal to the control terminal of the third transistor thereby allowing a current to pass between the first and second controlled terminals of the third transistor;
• voltage clamping means comprising:
• a first PNP transistor having an emitter connected to the base of the first NPN transistor and a collector connected to the common reference terminal;
• and
• a clamp circuit bias means connected between the base of the second NPN transistor and a base of the first PNP transistor for providing a bias voltage between the bases of the second NPN transistor and the first PNP transistor that has a magnitude that is less than a voltage equivalent to a magnitude of one diode drop;
• and
• switching means connected to the first input terminal and the base of the first NPN transistor for providing a base drive signal to the base of the first NPN transistor based on the TTL compatible signal voltage thereby selectively allowing current to pass between the collector and emitter of the first NPN transistor producing a current mode logic signal at the collector of one of the first NPN transistor collector and the second NPN transistor collector.

A logic translator suited for low supply voltage operation, the logic translator being capable of receiving a TTL compatible signal and providing a current mode logic signal based thereon, the logic translator comprising:

• a first input terminal for receiving a TTL compatible signal having a TTL compatible signal voltage relative to a common reference terminal;
• voltage reference means for providing a reference voltage relative to the common reference terminal, the voltage reference means comprises a first resistor, a Schottky diode and a PN junction connected together in series between the common reference terminal and a current source with the reference voltage being equal to the sum of the voltage drops across each of the Schottky diode, the PN junction and the first resistor, the first resistor having a voltage drop thereacross that has a magnitude that is less than a voltage equivalent to a magnitude of one diode drop;
• current switch means for selectively allowing current flow in a first and second collector circuit, the current switch means comprising:
• first and second NPN transistors having emitters connected together with each NPN transistor having a base and with the first NPN transistor having a collector connected to the first collector circuit and the second NPN transistor having a collector connected to the second collector circuit and with the second NPN transistor having a base connected to the reference voltage means;
• a third NPN type transistor having an emitter connected to the common reference terminal and having a collector connected to the emitters of each of the first and second NPN transistors;
• and
• the third NPN transistor having a base connected to a region of the PN junction and a region of the PN junction being connected to the common reference terminal to provide a control signal to the base of the third NPN transistor thereby allowing a current to flow between the collector and emitter of the third NPN transistor;
• current source means having a first PNP transistor connected between the supply terminal and the base of the first NPN transistor, a second PNP transistor connected to the supply terminal, and a fourth NPN transistor connected between the second PNP transistor and the common reference terminal, the first and second PNP transistors being arranged as a current mirror with the current in the first PNP transistor being related to the current in the second PNP transistor, the base of the fourth NPN transistor being connected to the region of the PN junction;
• and
• switching means connected to the first input terminal and the base of the first NPN transistor for providing a base drive signal to the base of the first NPN transistor based on the TTL compatible signal voltage thereby selectively allowing current to pass between the collector and emitter of the first NPN transistor producing a current mode logic signal between the common reference terminal and one of the first NPN transistor collector and the second NPN transistor collector.