US 5,349,246 A · Input buffer with hysteresis characteristics

Abstract

An input buffer circuit is disclosed which has feedback hysteresis transistors having similar size characteristics as the drive transistors. The drive transistors are located in a first inverting CMOS stage, connected in conventional CMOS inverter fashion. The drains of the drive transistors are connected to the input of an inverter, the output of which drives the signal to elsewhere in the integrated circuit. A first hysteresis leg is provided, consisting of a plurality of p-channel transistors with their source/drain paths in series between the input of the inverter and a power supply voltage; the gate of at least one of the p-channel hysteresis transistors is coupled to the output of the inverter, and the gates of those of the hysteresis transistors that are not coupled to the inverter output are biased to ground. A second hysteresis leg of n-channel hysteresis transistors, similarly but complementarily configured, is provided between ground and the inverter input. The hysteresis transistors each have channel lengths substantially the same as the drive transistors, thus reducing the capacitive load at the output of the inverter and also ensuring good tracking over process variations; the channel widths of the hysteresis transistors may also be made sufficiently wide to avoid small width effects, and thus also provide improved tracking.

Claims21

Dependent claims

A buffer circuit, comprising:

a first drive transistor of the field-effect type, having a gate for receiving an input signal, having a source biased by a first reference voltage, and having a drain;
a driver circuit having an input coupled to the drain of said first drive transistor, and having an output;
a first plurality of hysteresis transistors of the field-effect type, said first plurality of hysteresis transistors having their source-drain paths connected in series between the input of the driver circuit and a second reference voltage, a first one of said first plurality of hysteresis transistors having its gate coupled to the output of said driver circuit, and a second one of said first plurality of hysteresis transistors has its gate biased to a voltage sufficient to place it in a conductive state, so that the source-drain paths of said first plurality of hysteresis transistors are conductive responsive to the output of said driver circuit being at a first logic state;
wherein the logic state corresponding to said first reference voltage, when presented to the input of said driver circuit, causes said driver circuit to place its output at a second logic state;
and wherein the channel length of each of said first plurality of hysteresis transistors is approximately the same as that of said first drive transistor.

2 more elements

Dependencies are inferred from the claim text.

Input buffer with hysteresis characteristics

Life of this patent

Input buffer with hysteresis characteristics

Life of this patent

Abstract

Claims21