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US 5,349,243 AGranted
Latch controlled output driver
AssigneeSGS-Thomson Microelectronics S.A.
InventorDavid C. McClure
Life of this patent
Estimating the term…
Abstract
An output driver includes a pull-up and a pull-down transistor in series between an upper and a lower power supply voltage. Each transistor is controlled by a latch connected to its gate. Control transistors are cross-coupled between inputs to the latches and a power supply voltage to force at least one of the latches to be in a known state. This prevents both of the transistors from turning on simultaneously.
Claims21
A latch controlled output driver circuit comprising:
- an output driver circuit including a pull-up transistor and a pull-down transistor, wherein the pull-up transistor has a drain connected to an upper power supply voltage and a source connected to a drain of the pull-down transistor and the pull-down transistor has a source connected to a lower power supply voltage;
- a first latch circuit having an input and an output, wherein the output of the first latch circuit is connected to a gate of the pull-up transistor;
- a second latch circuit having an input and an output, wherein the output of the second latch circuit is connected to a gate of the pull-down transistor;
- a first gate having an output connected to the input of the first latch circuit;
- a second gate having an output connected to the input of the second latch circuit;
- a first control transistor having a source connected to the upper power supply voltage, a drain connected to the input of the first latch circuit, and a gate connected to the input of the second latch circuit;
- and
- a second control transistor having a source connected to the upper power supply voltage, a drain connected to the input of the second latch circuit, and a gate connected to the input of the first latch circuit.
5 more elements
A memory comprising:
- a plurality of memory groups having a plurality of outputs;
- and
- a data bus circuit having a plurality of inputs connected the plurality of outputs, the data bus circuit having a latch controlled output driver circuit that includes:
- an output driver circuit including a pull-up transistor and a pull-down transistor, wherein the pull-up transistor has a drain connected to an upper power supply voltage and a source connected to a drain of the pull-down transistor and the pull-down transistor has a source connected to a lower power supply voltage;
- a first latch circuit having an input and an output, wherein the output of the first latch circuit is connected to a gate of the pull-up transistor;
- a second latch circuit having an input and an output, wherein the output of the second latch circuit is connected to a gate of the pull-down transistor;
- a first gate having an output connected to the input of the first latch circuit;
- a second gate having an output connected to the input of the second latch circuit;
- a first control transistor having a source connected to the upper power supply voltage, a drain connected to the input of the first latch circuit, and a gate connected to the input of the second latch circuit;
- and
- a second control transistor having a source connected to the upper power supply voltage, a drain connected to the input of the second latch circuit, and a gate connected to the input of the first latch circuit.
8 more elements
A control circuit for controlling first and second output transistors in a driver circuit comprising:
- first and second latches, each latch having an output and an input, the first latch having an output connected to a gate of the first output transistor, and the second latch having an output connected to a gate of the second output transistor;
- first and second gates, each gate having an output and an input, the output of the first gate being connected to the input of the first latch and the output of the second gate being connected to the input of the second latch;
- and
- a regulation circuit connected to the latch inputs for preventing both inputs from simultaneously having a selected state, wherein the selected state at a latch inputs causes a corresponding output transistor to be turned on.
1 more element
Dependencies are inferred from the claim text.