Integrable MOS and IGBT devices having trench gate structure

A power MOSFET device comprising

• a semiconductor body having first and second major opposing surfaces with a first doped region of a first conductivity type therebetween,
• first and second double diffused regions formed in said first doped region, said first and second double diffused regions being spaced apart and abutting said first surface,
• first and second gate electrodes extending from said first surface into said first doped region, said first gate electrode being adjacent to said first double diffused region and spaced therefrom by an electrically insulative layer, said second gate electrode layer being adjacent to said second double diffused region and spaced therefrom by an electrically insulative layer,
• said first region extending to said first surface between said first and second gate electrodes and separated therefrom by an electrically insulative layer of suitable thickness for voltage blocking, and
• a drain region of said first conductivity type in said first doped region between said gate electrodes and abutting said first surface,
• said first and second double diffused regions comprising source and channel regions of said device.

An insulated gate bipolar transistor (IGBT) device comprising

• a semiconductor body having first and second major opposing surfaces with a first doped region of a first conductivity type therebetween,
• first and second double diffused regions formed in said first doped region, said first and second double diffused regions being spaced apart and abutting said first surface,
• first and second gate electrodes extending from said first region into said first doped region, said first gate electrode being adjacent to said first double diffused region and spaced therefrom by an electrically insulative layer, said second gate electrode being adjacent to said second double diffused region and spaced therefrom by an electrically insulative layer,
• said first region extending towards said first surface between said first and second gate electrodes and separated from said first and second gate electrodes by an electrically insulative layer of suitable thickness for voltage blocking, and
• a doped region of a second conductivity type in said first doped region between said first and second gate electrodes and functioning as an anode, said first and second double diffused regions functioning as cathodes and channel regions of said device.

A method of fabricating a power semiconductor device which is integrable in an integrated circuit comprising the steps of

• a) providing a semiconductor body having first and second major opposing surfaces with a first doped region of a first conductivity type therebetween,
• b) forming a first surface region in said first doped region with dopant of a second conductivity type, said surface region abutting said first surface,
• c) forming a second surface region of said first conductivity type in said first surface region, said second surface region abutting said first surface,
• d) forming a trench through said first surface region, said second surface region, and into said first doped region, said trench having exposed sidewalls and a bottom surface,
• e) forming electrically insulative layers on said sidewalls,
• f) forming conductive layers over said electrically insulative layers on said sidewalls,
• g) forming electrically insulative layers of suitable thickness for voltage blocking on said conductive layers,
• h) filling said trench with semiconductor material selectively epitaxially grown said bottom surface, and
• i) doping a surface portion of said semiconductor material in said trench.

A microelectronic gated device comprising

• a monocrystalline semiconductor substrate having a trench therein at one face thereof, said trench including a trench sidewall;
• a relatively thin first insulating layer on said trench sidewall for gate oxide;
• a gate electrode on said relatively thin first insulating layer;
• a relatively thick second insulating layer on said gate electrode for voltage blocking;
• a monocrystalline semiconductor region on said relatively thick second insulating layer, and extending from said substrate to said one face;
• first contact means for electrically contacting said monocrystalline semiconductor region at said one face;
• and
• second contact means for electrically contacting said monocrystalline semiconductor substrate at said one face.