US 5,348,904 AGranted

Method of fabricating semiconductor memory device including an improved substrate structure

AssigneeNEC Corporation

InventorKuniaki Koyama

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Abstract

The invention provides a semiconductor substrate structure for semiconductor integrated circuit devices including a memory cell array area involving both stacked capacitors and transistors and a peripheral circuit area involving transistors. A portion of the device in the memory cell area has a larger thickness than that of the peripheral circuit area. The transistors involved in the memory cell array area possess different properties from that of the transistors involved in the peripheral circuit area. The substrate structure has a surface region comprising a first impurity concentration region underlying a recessed portion in the memory cell array area and an opposite region having a second impurity concentration from that of the high impurity concentration region so that a surface in the memory cell area exists at a lower level than that of a surface in the peripheral area. The recessed portion makes difference in surface levels of the device reduced, resulting in fine patterns of photo-lithography promoting high integration. Both the first and second impurity concentrations are so determined as to allow the transistors involved in the both areas to exhibit best performances and an excellent properties respectively.

Claims4

Dependent claims

A method of forming a semiconductor substrate for a semiconductor integrated circuit device including a first multi-layer structure having a thickness formed in an array area and a second multi-layer structure formed in a peripheral area, said first structure being thicker than said second multi-layer structure, said method comprising the steps of:

forming a first insulation film over an entire surface of a semiconductor substrate having an impurity concentration of a first conductivity type, said substrate having an array area and a peripheral area;
selectively forming a second insulation film on said first insulation film in said peripheral area;
forming a well region in the surface of said substarate and in said array area by a selective ion-implantation of an impurity of a conductivity type which is opposite to the conductivity type of said substrate;
forming a high impurity concentration planar region in said well region by a selective ion-implantation of an impurity of a conductivity type which is the same conductivity type as the impurity as said substrate;
and
forming a thick insulation film in said array area portion of said first insulation film so as to depress said high impurity concentration planar region;
and
removing said first and second insulation films and said thick insulation film to form a recessed portion in said array area.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/993,382Filed 18 Dec 1992
Priority: JP 3-35607020 Dec 1991
Granted: 20 Sep 1994
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10B 12/01
Dynamic random access memory [DRAM] devices: manufacture or treatment
H10B 12/033
Making the capacitor or connections thereto: the capacitor extending over the transistor
H10D 84/0133
Manufacturing their source or drain regions, e.g. silicided source or drain regions: manufacturing common source or drain regions between multiple…
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe

Family

No related US applications are recorded in the indexed filing history.

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