Transistor fabrication methods using overlapping masks

A method for forming a transistor having a first region, a second region of the same conductivity type as said first region, and a third region separating said first and second regions, said method comprising the steps of:

• forming a first layer over said third region;
• introducing a dopant of said conductivity type into said first and second regions while said first layer masks said third region;
• forming a second layer over said first, second and third regions and over said first layer;
• selectively removing a portion of said second layer so that a remaining portion of said second layer overlies a first portion of said first region which first portion is adjacent said third region:
• and
• introducing a dopant of said conductivity type into a second portion of said first region and into said second region while said first and second layers mask said third region and said first portion of said first region, wherein:
• one of said first and second regions is a source region of said transistor, the other one of said first and second regions is a drain region of said transistor, and said third region is a channel region of said transistor;
• said first, second and third regions are regions of a semiconductor layer formed over a gate of said transistor;
• each of said first and second regions extends over said gate;
• and
• said second portion of said first region is laterally spaced from said gate.

A method for doping a transistor having a first region, a second region and a third region separating said first and second regions, said method comprising the steps of:

• forming a mask over said third region;
• introducing a dopant into said first and second regions;
• forming a conformal layer of material over said mask so as to completely cover said first, second and third regions;
• and
• introducing a dopant into said first and second regions through said conformal layer while said conformal layer completely covers said first and second regions and while a portion of said conformal layer on sidewalls of said mask masks a portion of said first and second regions.

A method for forming a memory cell comprising transistors T1, T2, T3 and T4, said method comprising the steps of:

• forming said transistor T1 having electrodes S1 and D1 and a gate G1, and forming said transistor T2 having electrodes S2 and D2 and a gate G2;
• forming over said transistors T1 and T2:
• a first interconnect interconnecting said gate G1 and said electrode D2;
• and
• a second interconnect interconnecting said gate G2 and said electrode D1;
• forming an insulator over said first and second interconnects and said transistors T1 and T2;
• forming contact openings in said insulator to allow electrical contact to said first and second interconnects;
• forming a semiconductor layer over said insulator, said semiconductor layer contacting said first and second interconnects through said contact opening;
• forming a first mask over portions CH3 and CH4 of said semiconductor layer wherein said portions CH3 and CH4 are channel regions of, respectively, said transistors T3 and T4;
• introducing a dopant into portions S3, D3, S4, D4 of said semiconductor layer wherein one of said portions S3, D3 is a source region of said transistor T3 and the other one of said portions S3, D3 is a drain region of said transistor T3, and wherein one of said portions S4, D4 is a source region of said transistor T4 and the other one of said portions S4, D4 is a drain region of said transistor T4;
• forming a second mask over a part of said region D3 which part is adjacent said channel region CH3 and over a part of said region D4 which part is adjacent said channel region CH4;
• and
• introducing a dopant into said regions S3, S4 and into parts of said regions D3, D4 which parts are exposed by said first and second masks.

A method for fabricating a transistor, said method comprising the steps of:

• forming a gate of said transistor in or over a semiconductor substrate;
• after said gate forming step, forming a semiconductor layer over said substrate, said semiconductor layer including a first region and a second region spaced from said first region, wherein one of said first and second regions is a source region of said transistor and the other one of said first and second regions is a drain region of said transistor, said semiconductor layer further comprising a channel region separating said first and second regions;
• forming a first mask over said channel region;
• introducing a dopant into said first and second regions;
• removing said first mask;
• forming a second mask over said channel region and over a portion of said first region which portion is adjacent said channel region;
• and
• introducing a dopant into said second region and into a portion of said first region which portion is not overlain by said second mask.