Parallel processor and method of fabrication

A method of fabricating a parallel processor structure having a plurality of processor integrated circuit chips, a plurality of memory integrated circuit chips, with signal interconnection circuitization means therebetween, wherein

• a. the processor integrated circuit chips and the memory integrated circuited chips are mounted on a plurality of printed circuit cards and boards with a first processor integrated circuit printed circuit board having a first processor integrated circuit chip mounted thereon, a second processor integrated circuit printed circuit board having a second processor integrated circuit chip mounted thereon, a first memory integrated circuit printed circuit board having a first memory integrated circuit chip mounted thereon, and a second memory integrated circuit printed circuit board having a second memory integrated circuit chip mounted thereon;
• b. said printed circuit cards and boards are mounted on a plurality of circuitized flexible strips, said circuitized flexible strips having a signal interconnection circuitization portion with X-Y planar circuitization and vias and through holes for Z-axis circuitization, a terminal portion having means for joining a printed circuit board thereto, and a flexible, circuitized portion between said signal interconnection circuitization portion and said terminal portion, and
• c. said circuitized flexible strips being joined at a signal interconnection circuitization body portion having X-axis, Y-axis, and Z-axis signal interconnection between processor integrated circuit chips and memory integrated circuit chips and comprising a laminate of said circuitized flexible strips at their signal interconnection circuitization portions, whereby said circuitized flexible strips are laminated in physical and electrical connection at their signal interconnection circuitization portions and spaced apart at their terminal portions;
• said process comprising
• a. forming first and second laminates of copper, a dielectric, and a low coefficient of thermal expansion metal;
• b. photolithographically forming patterns in said copper and said low coefficient of thermal expansion metal layers;
• c. bonding the first and second laminates together;
• d. thereafter forming vias and through holes in said bonded first and second laminates, and circuitizing said vias and through holes.
• e. depositing joining metallurgy on said bonded laminates;
• and
• f. aligning at least a pair of bonded laminates with a layer of a chemically compatible polymeric dielectric with a relatively low first thermal transition therebetween in areas between a pair of laminates intended to be bonded and a layer of a chemically incompatible polymeric dielectric with a relatively high first thermal transition therebetween in areas between the laminates not intended to be bonded, and thermally bonding the laminates above the eutectic temperature of the joining metallurgy and the first thermal transition temperature of the chemically compatible dielectric and below the homogenized alloy melting temperature of the joining metallurgy and the first thermal transition temperature of the joining metallurgy.