US 5,347,645 AGranted

Time code interface

AssigneeThe United States of America as represented by the Secretary of the Navy

InventorJames D. Perry

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Abstract

A modularized Time Code Interface (TCI) used to time tag asynchronous eve. Input and output connectors provide modularity in that the TCI may be readily plugged into or removed from a system. The TCI utilizes programmable memory for storing time intervals that are used in producing time of day data associated with the occurrence of an asynchronous event.

Claims5

Dependent claims

An apparatus for associating a time with an event, comprising:

first counter means for receiving a first repetitive clock signal of a first frequency, said first counter means counting the first repetitive clock signal for a predetermined interval of time, said first counter means outputting a first multi-bit digital signal representing a duration of said predetermined interval of time;
buffer means having an input for receiving a second multi-bit digital signal representing a current time of day (TOD), said second multibit digital signal having a lesser degree of resolution than said first multibit digital signal;
second counter means for receiving a second repetitive clock signal of a second frequency, said second frequency being less than said first frequency;
storage means having a first plurality and a second plurality of addressable locations, said storage means having a plurality of least significant address inputs coupled to an output of said second counter means and at least one most significant bit address input coupled to a signal expressive of a repetitively reoccurring time interval having a first logic state and a second logic state, said storage means storing at each location within said first and said second plurality of addressable locations a value expressive of a time, said storage means being responsive to the state of said repetitively reoccurring time interval and to said plurality of least significant address inputs to form a multi-bit address for reading out a stored value expressive of a time;
comparison means having a first input coupled to an output of said storage means and a second input coupled to a time signal expressive of a current time, said comparison means comprising means for comparing said output of said storage means to said time signal expressive of a current time and for asserting a control signal in response to the time signal equaling said stored value being outputted by said storage means, said control signal being coupled to said buffer means for causing said output of said buffer means to be enabled, said control signal being further coupled to said first counter means for resetting said first counter means, and said control signal also being coupled to said buffer means for enabling said buffer means;
and
sequencing means including a counter circuit, said sequencing means serving to sequence the addresses of the storage means and having a first input coupled to said second repetitive clock signal and a second input coupled to a third repetitive clock signal wherein said third repetitive clock signal has a frequency that is less than that of said first and second repetitive clock signals.

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Dependencies are inferred from the claim text.

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Abstract

An apparatus for associating a time with an event, comprising:

first counter means for receiving a first repetitive clock signal of a first frequency, said first counter means counting the first repetitive clock signal for a predetermined interval of time, said first counter means outputting a first multi-bit digital signal representing a duration of said predetermined interval of time;
buffer means having an input for receiving a second multi-bit digital signal representing a current time of day (TOD), said second multibit digital signal having a lesser degree of resolution than said first multibit digital signal;
second counter means for receiving a second repetitive clock signal of a second frequency, said second frequency being less than said first frequency;
storage means having a first plurality and a second plurality of addressable locations, said storage means having a plurality of least significant address inputs coupled to an output of said second counter means and at least one most significant bit address input coupled to a signal expressive of a repetitively reoccurring time interval having a first logic state and a second logic state, said storage means storing at each location within said first and said second plurality of addressable locations a value expressive of a time, said storage means being responsive to the state of said repetitively reoccurring time interval and to said plurality of least significant address inputs to form a multi-bit address for reading out a stored value expressive of a time;
comparison means having a first input coupled to an output of said storage means and a second input coupled to a time signal expressive of a current time, said comparison means comprising means for comparing said output of said storage means to said time signal expressive of a current time and for asserting a control signal in response to the time signal equaling said stored value being outputted by said storage means, said control signal being coupled to said buffer means for causing said output of said buffer means to be enabled, said control signal being further coupled to said first counter means for resetting said first counter means, and said control signal also being coupled to said buffer means for enabling said buffer means;
and
sequencing means including a counter circuit, said sequencing means serving to sequence the addresses of the storage means and having a first input coupled to said second repetitive clock signal and a second input coupled to a third repetitive clock signal wherein said third repetitive clock signal has a frequency that is less than that of said first and second repetitive clock signals.

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