Circuit for generating addresses for buffering and reading the data from a CD-ROM and method therefor

A circuit for generating address data for accessing a buffer memory for writing and reading parity data, said circuit comprising:

• a write address generator for generating write address data in response to a received write control signal and received clock pulses;
• a read address generator for generating read address data in response to said a read control signal and said received clock pulses, said read address generator comprising:
• a read control signal generator for generating an output code word sequence number, a first clear signal, a second clear signal, first read clock pulses, second read clock pulses, a first read load signal and a second read load signal,
• a first read counter for generating first read address data by counting said first read clock pulses in response to one of said first clear signal and said first read load signal,
• a second read counter for generating second read address data by counting said second read clock pulses in response to one of said second clear signal and said second read load signal,
• an adder for generating summation address data by adding said output code word sequence number and said second read address data,
• modular operator means for generating a modular address value in response to said summation address data, and
• selection means for outputting, as said read address data, said first and second read address data or said modular address value and said output code word sequence number;
• and
• read/write mode selection means for receiving said write address data generated by said write address generator and said read address data generated by said read address generator and for selecting one of said write address data and said read address data for output to said buffer memory in response to one of a write mode selection signal and a read mode selection signal.

A circuit for generating first and second write address data for accessing a buffer memory of a CD-ROM for writing P-parity data and Q-parity data, said circuit comprising:

• an initial value generator for generating a first initial value, a second initial value and an initialization control signal;
• a write control signal generator for receiving a timing signal comprised of command data, for processing said command data for generating first clock pulses, second clock pulses, a first load signal and a second load signal in response to said initialization control signal;
• a first write counter having a first clock input for receiving said first clock pulses, a first load input for receiving said first load signal, and an initialization input for receiving said first initial value, said first write counter for generating said first write address data by being initialized for counting said first clock pulses up from said first initial value in response to said first load signal;
• a second write counter having a second clock input for receiving said second clock pulses, a second load input for receiving said second load signal, and an initialization input for receiving said second initial value, said second write counter for generating said second write address data by being initialized for counting said second clock pulses up from said second initial value in response to said second load signal;
• and
• address decoder means for generating a signal for controlling said initial value generator by receiving and decoding said first and second write address data.

A circuit for generating address data for accessing a buffer memory of a CD-ROM for reading P-parity data and Q-parity data, said circuit comprising:

• a read control signal generator for receiving a timing signal comprised of command data, for processing said command data for generating a code word sequence number, a first clear signal, a second clear signal, first read clock pulses, second read clock pulses, a first read load signal and a second read load signal;
• a first read counter for generating first read address data by counting said first read clock pulses in response to one of said first clear signal and said first read load signal;
• a second read counter for generating second read address data by counting said second read clock pulses in response to one of said second clear signal and said second read load signal;
• an adder for generating summation address data by adding said output code word sequence number and said second read address data;
• modular operator means for generating a modular address value in response to said summation address data;
• and
• selection means for outputting, as said address data for accessing said buffer memory, said first and second read address data or said modular address value and said output code word sequence number.

A method for accessing a buffer memory of a CD-ROM said method comprising the steps of:

• generating first and second write address data for writing P-parity data and Q-parity data to said buffer memory, said generating step comprising the steps of;
• generating first and second initial values and an initializing signal in response to a initializing control signal,
• processing write command data of a timing signal for generating first and second clock pulses, and for generating first and second load signals in response to said initializing signal,
• loading said first initial value into a first counter in response to said first load signal and counting said first clock pulses up to a first count from said initial value, said first count forming said first write address data,
• loading said second initial value into a second counter in response to said second load signal and counting said second clock pulses up to a second count from said initial value, said second count forming said second write address data, and
• decoding said first and second counts for generating said initializing control signal.

A method for accessing a buffer memory of a CD-ROM said method comprising the steps of:

• generating read address signals for reading P-parity data and Q-parity data from said buffer memory, said read address signal generating step comprising the steps of;
• processing read command data of a timing signal for generating a code word sequence number, for generating first and second clock pulses, for generating first and second load signals and for generating first and second clear signals,
• supplying said first clear signals, said first load signals and said first clock pulses to a first counter,
• supplying said second clear signals, said second load signals and said second clock pulses to a second counter,
• counting said first clock pulses to generate first read address data,
• counting said second block pulses to generate second read address data,
• adding said code word sequence number and said second read address data for generating summation data,
• applying a modular value to said summation data for generating third read address data,
• supplying said first and third read address data to a first selection means,
• supplying said code word sequence number and said second read address data to a second selection means, and
• controlling said first and second selection means for selectively outputting one of a first output comprised of said first and second read address data and a second output comprised of said third read address data and said code word sequence number, in response to a selection signal.