Data processor which efficiently accesses main memory and input/output devices
AssigneeNEC Corporation
InventorsYasushi Ooi, Yoshiyuki Miki
Life of this patent
Estimating the term…
Abstract
A data processor which includes at least a central processing unit adapted to execute virtual memory management. The central processing unit internally includes a translation lookaside buffer (TLB) for translating a given virtual address into a corresponding real address. The TLB also generates a distinction signal indicating whether the translated real address designates a main memory or an external input/output device. In response to the distinction signal, a control signal generator outputs a set of input/output control signals for the access of the type designated by the distinction signal.
Claims8
A data processor with memory mapped input/output structure in which a portion of an address space is allocated to a main memory and another portion of the address space is allocated to a plurality of external input/output devices and which includes at least a central processing unit adapted to execute virtual memory management, wherein the improvement comprises:
- a) address translation means, internally provided in the central processing unit, for translating a given virtual address into a corresponding real address;
- b) means, associated with the address translation means and internally provided in the central processing unit, for generating a distinction signal indicating whether the translated real address designates said main memory or one of said external input/output devices, the distinction signal also directly specifying the specific one of said external input/output devices to be accessed when the translated real address designates one of said external input/output devices;
- and
- c) means, which is internally provided in the central processing unit and which receives the distinction signal, for generating a set of input/output control signals to directly access said external input/output devices.
A data processor with memory mapped input/output structure in which a portion of an address space is allocated to a main memory and another portion of the address space is allocated to at least one external input/output device and which comprises:
- a) an instruction execution unit coupled to an address bus;
- b) an instruction analyzer, which receives a given instruction and outputs to the instruction execution unit a decoded instruction which can be executed by the instruction execution unit, and which generates information necessary for calculation of the effective address of an operand;
- c) an effective address calculation unit, which receives the information from the instruction analyzer, for generating an effective address;
- d) an address transformation unit which receives the effective address and generates a real address;
- and
- e) a main memory coupled to receive the real address from the address transformation unit and also coupled to send read data to the instruction execution unit;
- where the address transformation unit includes a translation lookaside buffer adapted to store a plurality of data sets, each of which contains:
- one virtual address;
- a corresponding real address;
- and access distinction information, which indicates whether the real address is allocated to the main memory or an external input/output device, and which is used to directly determine whether or not the virtual address indicates access to an external input/output device.
Dependencies are inferred from the claim text.