Bit aligned data block transfer method and apparatus
AssigneeNetwork Computing Devices, Inc.
InventorsJohn R. Providenza, Lee Boekelheide
Life of this patent
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Abstract
The number of required clock periods in a bit aligned block transfer operation may be reduced by analyzing the logical relationship between source, destination and pattern operands prior to fetching these operands from memory. If the result of the raster operation can be determined without actually using the value of any of the operands, the result is provided without reading memory values. When the raster operation will have no effect on the existing destination operand, the write operation is also canceled.
Claims11
A system for transfer of graphics data in a memory, said transferred data being defined according to a predetermined logic expression representative of a logic relationship involving first and second operands, each operand being representative of respective data with at least one of said first and second operands being representative of graphics data in said memory, said system comprising:
- image modification means for managing said memory for selectively effecting a given memory operation representing said predetermined logic expression with respect to said operands and providing an image output per said predetermined logic expression, and
- means for identifying, before engaging at least one of said first and second operands, the logical effect that one of said operands will have on the image output per said predetermined logic expression and causing said image modification means to manage said memory with respect to other than said one of said operands when it is determined said one of said operands fails to have a logical effect on said output.
A system for transfer of graphics data in a memory, said transferred data being defined according to a predetermined logic expression representative of a logic relationship between first, second and third operands, each operand being representative of respective data with at least one of said first, second and third operands being representative of graphics data in said memory, said system comprising:
- image modification means for managing said memory for selectively effecting a given operation representing said predetermined logic expression with respect to said first, second, and third operands and for providing an image output per said predetermined logic expression, and
- means for identifying, before engaging said first and second operands, the logical effect that one of said first and second operands will have on the image output per said predetermined logic expression, and causing said image modification means to manage said memory with respect to other than said one of said first and second operands when it is determined said one of said first and second operands fails to have a logical effect on said image output.
A graphics system for associating a plurality of operands including at least first and second image operands, each operand being representative of graphics data, said system comprising:
- image modification means for selectively effecting a predetermined raster logic operation with respect to said plurality of operands and providing an image output, and
- primary means for determining, in a first determination before engaging said first operand, the logical effect that said first operand will have on the image output per said predetermined raster logic operation and accessing said first operand for employment by said image modification means when it is determined that it has a positive logical effect on the image output per said predetermined raster logic operation.
Dependencies are inferred from the claim text.