Boundary-scan enable cell with non-critical enable path

A boundary-scan cell for testing a system logic and its pin connections comprising:

• a monitoring circuit including a NOR gate having critical enable term and non-critical term inputs and having a term output and a test output for comparison with a twin cell;
• a first multiplexer having critical enable term, non-critical term, and shift inputs;
• a sampling circuit coupled between the term output of the monitoring circuit and the non-critical term input of the first multiplexer including a second multiplexer having a term input and a previous cell contents input, a shift register coupled to the output of the second multiplexer including an inverter coupled to the output of the second multiplexer and a D-type flip-flop coupled to the output of the inverter, and a latch coupled between the output of the shift register and the non-critical term input of the first multiplexer;
• and
• a test control circuit including a first subcircuit coupled between the latch output and the non-critical term input of the first multiplexer including a first NAND gate having latch and first test inputs, a second NAND gate having first NAND gate and second test inputs, and a third NAND gate having second NAND gate and third test input and a non-critical term output, and a second subcircuit coupled between the system logic and the shift input of the first multiplexer including an OR gate having non-critical term and third test inputs.