Row decoder for NAND-type ROM

A CMOS decoder circuit for a NAND-type memory array, comprising:

• a virtual ground node;
• multiple first N-channel transistor each connected between said virtual ground node and a respective active-low selection line;
• one or more second N-channel transistors each connected between said virtual ground node and a respective parcel-select line;
• one or more third N-channel transistors each connected between said virtual ground node and a respective row-select subcircuit moiety, and each connected to be controlled by a respective line of said fourth bus;
• and
• multiple fourth P-channel transistors each operatively connected between a respective one of said third transistors and a respective one of said row-select lines;
• wherein multiple ones of said fourth transistors are operatively connected in parallel to each of said third transistors.

A CMOS integrated circuit, comprising:

• an array of memory cells which are NAND-connected in parcels, and which are connected to be accessed by row-select lines and pared-select lines;
• predecode logic;
• a first bus including multiple virtual ground lines, said predecode logic being connected to drive a selected one of the lines of said first bus low;
• a second bus including multiple preselect lines, said predecode logic being connected to drive a selected one of the lines of said second bus high;
• a third bus including multiple parcel-select lines, said predecode logic being connected to drive a selected one of the lines of said third bus high;
• a fourth bus including multiple quadrant-select lines, said predecode logic being connected to drive a selected one of the lines of said fourth bus high;
• a fifth bus including multiple row-select lines, said predecode logic being connected to drive a selected one of the lines of said fifth bus low;
• multiple blocks of selection logic, each including
• a virtual ground node;
• multiple first N-channel transistors all connected in series between said virtual ground node and a respective one of the lines of said first bus, and each connected to be controlled by a respective line of said second bus;
• one or more second N-channel transistors each connected between said virtual ground node and a respective parcel-select line, and each connected to be controlled by a respective line of said third bus;
• one or more third N-channel transistors each connected between said virtual ground node and a respective row-select subcircuit moiety, and each connected to be controlled by a respective line of said fourth bus;
• and
• multiple fourth P-channel transistors each operatively connected between a respective one of said third transistors and a respective one of said row-select lines;
• wherein multiple ones of said fourth transistors are operatively connected in parallel to each of said third transistors.