Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device comprising:

• a memory cell array having at least first and second blocks, each block including a plurality of electrically erasable and programmable memory cells,
• voltage lowering means for lowering an externally applied predetermined high voltage in sufficient range in which a tunnel phenomenon occurs in said electrically erasable and programmable memory cells in a data erase mode,
• first high voltage applying means for collectively applying high voltage lowered by said voltage lowering means to all of said electrically erasable and programmable memory cells included in said first block in said data erase mode, and
• second high voltage applying means for collectively applying the high voltage lowered by said voltage lowering means to all of said memory cells included in said second block in said data erase mode;
• means for reading storage data of said memory cells included in said first and second blocks in said data erase mode;
• and
• means responsive to the data read by said reading means for controlling said first and second high voltage applying means to be individually enabled or disabled.

A nonvolatile semiconductor memory device comprising:

• a memory cell array including a plurality of electrically erasable and programmable memory cells,
• voltage lowering means including;
• (a) an output node,
• (b) electric path means for transmitting an externally applied predetermined high voltage to said output node,
• (c) means for making a comparison between a predetermined reference voltage lower than said predetermined high voltage and a voltage appearing at said output node and for controlling said electric path means using said comparison, and
• means for applying the voltage appearing at the output node of said voltage lowering means to said memory cell in order to erase data stored in said memory cell.

A nonvolatile semiconductor memory array, comprising:

• a plurality of electrically erasable and programmable memory cells,
• voltage lowering means including:
• (a) an output node,
• (b) a field effect semiconductor element having a first conduction terminal for receiving an externally applied predetermined high voltage, a second conduction terminal connected to said output node, and a control terminal;
• and
• (c) operational amplifier means having a first input terminal for receiving a predetermined reference voltage lower than said predetermined high voltage, a second input terminal connected to said output node, and an output terminal connected to said control terminal of said field effect semiconductor element, and
• means for applying the voltage appearing at the output node of said voltage lowering means to said memory cell in order to erase data stored in said memory cell.

A nonvolatile semiconductor memory device, comprising:

• a first supply terminal to which a first supply voltage is applied;
• a second supply terminal to which a ground potential is applied;
• a memory cell array including a plurality of electrically erasable and programmable memory cells, each electrically erasable and programmable memory cell having a source electrode, a drain electrode connected to a corresponding bit line, a floating gate, and a control gate connected to a corresponding word line;
• means for applying to the control gate of said electrically erasable and programmable memory cell the first supply voltage applied to said first supply terminal at the time of data writing, and
• means, having voltage converting means receiving the first supply voltage applied to said first supply terminal for converting the received first supply voltage into a second voltage having an intermediate value between the received first supply voltage and the ground voltage applied to said second supply terminal, for applying the second voltage from said voltage converting means to said source electrode of said electrically erasable and programmable memory cell so that a tunnel phenomenon occurs in a gate insulating film located beneath said floating gate when electrons stored in the floating gate of said electrically erasable and programmable memory cell are drawn out to said source electrode of said cell.

A nonvolatile semiconductor memory device, comprising:

• a plurality of electrically erasable and programmable memory cells, each electrically erasable and programmable memory cell having a source electrode, a drain electrode, and a floating gate;
• erasing voltage applying means for applying a predetermined voltage to the source electrode of said plurality of electrically erasable and programmable memory cells to be erased, said erasing voltage applying means including temporarily storing means receiving a set signal and a reset signal and providing an erase mode signal in response to the set signal and not providing erase mode signal in response to the reset signal and an output from said temporarily storing means and responsive to the erase mode signal from said temporarily storing means for applying said predetermined voltage as received to the source electrode of said plurality of electrically erasable and programmable memory cells;
• and
• controlling means for providing said set signal to the temporarily storing means in said erasing voltage applying means when there exist electrically erasable and programmable memory cells in an unerased state as a result of reading the data stored in said plurality of electrically erasable and programmable memory cells after data erase mode when data stored in said plurality of electrically erasable and programmable memory cells are erased during a predetermined period.

A nonvolatile semiconductor memory device, comprising:

• a memory cell array having a plurality of blocks, each block including a plurality or electrically erasable and programmable memory cells, each electrically erasable and programmable memory cell having a source electrode, a drain electrode and a floating gate;
• a plurality of erasing voltage applying means provided corresponding to said plurality of blocks for applying a predetermined voltage to the source electrode of said plurality of electrically erasable and programmable memory cells when the data stored in plurality of electrically erasable and programmable memory cells in the corresponding block are to be erased, each of the erasing voltage applying means including temporarily storing means receiving a set signal and a reset signal and providing an erase mode signal in response to the set signal and not providing said erase mode signal in response to the reset signal, and switching means receiving said predetermined voltage and an output from said temporarily storing means and responsive to the erase mode signal from said temporarily storing means for applying said predetermined voltage as received to the source electrode of said plurality of electrically erasable and programmable memory cells;
• and
• controlling means for providing a set signal to the temporarily storing means of said erasing voltage applying means corresponding to the block in which there exist electrically erasable and programmable memory cells in an unerased state as a result of reading the data stored in said plurality of electrically erasable and programmable memory cells after data erase mode in which data stored in said plurality of electrically erasable and programmable memory cells in said each block is erased during a predetermined time period.

A nonvolatile semiconductor memory device, comprising:

• a plurality of electrically erasable and programmable memory cells, each electrically erasable and programmable memory cell having a pair of main electrodes and a floating gate;
• erasing voltage applying means for applying a predetermined voltage to one of said pair of main electrodes in said plurality of electrically erasable and programmable memory cells when electrons stored in the floating gate of said electrically erasable and programmable memory cells are drawn out, said erasing voltage applying means including temporarily storing means receiving a set signal and a reset signal and providing a predetermined voltage generating signal in response to the set signal and not providing said predetermined voltage generating signal in response to the reset signal, and switching means receiving said predetermined voltage and output from said temporarily storing means for applying said predetermined voltage as received to one of the pair of main electrodes of said plurality of electrically erasable and programmable memory cells;
• and
• controlling means for providing said set signal to the temporarily storing means of said erasing voltage applying means when electrons stored in the floating gates of said electrically erasable and programmable memory cells are insufficiently drawn out as a result of reading data stored in said plurality of electrically erasable and programmable memory cells after data stored in said plurality of electrically erasable and programmable memory cells has been drawn out during a predetermined period.

A nonvolatile semiconductor memory device, comprising:

• a memory cell array having a plurality of blocks, each block including a plurality of electrically erasable and programmable memory cells, each electrically erasable and programmable memory cell having a pair of main electrodes and a floating gate;
• a plurality of erasing voltage applying means provided corresponding to said plurality of blocks for applying a predetermined voltage to one of the pair of main electrodes of said plurality of electrically erasable and programmable memory cells when electrons stored in the floating gate of the plurality of electrically erasable and programmable memory cells to cause electrons stored in the floating gate of the plurality of in the corresponding block to be drawn out, each of the erasing voltage applying means including temporarily storing means receiving a set signal and a reset signal and providing a predetermined voltage generating signal in response to the set signal and not providing said predetermined voltage generating signal in response to the reset signal, and switching means receiving said predetermined voltage and an output from said temporarily storing means and responsive to the predetermined voltage generating signal from said temporarily storing means for applying said predetermined voltage as received to one of the pair of main source electrodes of said plurality of electrically erasable and programmable memory cells;
• and
• controlling means for providing a set signal to the temporarily storing means of said erasing voltage applying means corresponding to the block in which electrons stored in the floating gate of the electrically erasable and programmable memory cells have been insufficiently drawn out as a result of reading the data stored in said plurality of electrically erasable and programmable memory cells after electrons stored in said plurality of electrically erasable and programmable memory cells in said each block were drawn out during a predetermined time period.