Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy

A method of preconditioning and verifying the preconditioning of a first memory cell shorted to a second memory cell in a nonvolatile semiconductor memory array including a multiplicity of normal memory cells, each memory cell having a threshold voltage and a gate, preconditioning raising the threshold voltage of the first memory cell and the second memory cell to a level sufficient to prevent their leaking current during erase verification of normal memory cells, the method comprising the steps of:

• a) applying a first preconditioning pulse to the first memory cell and the second memory cell in parallel;
• b) reading the first memory cell by applying a first gate voltage level to the gates of the first memory cell and the second memory cell;
• c) reading a shorted reference cell having a gate and a shorted cell precondition reference voltage level by applying a second gate voltage level to the gate of the shorted reference cell, the second gate voltage level being less than the first gate voltage level, the shorted cell precondition reference voltage being lower than a normal cell precondition reference voltage above which the threshold voltages of normal memory cells are raised by preconditioning;
• d) comparing the threshold voltage of the first memory cell to the shorted cell precondition reference voltage to determine whether the threshold voltage of the first memory cell is greater than the shorted cell precondition reference voltage;
• and
• e) repeating steps a) through d) until the threshold voltages of the first memory cell and the second memory cell are greater than the shorted cell precondition reference voltage.