US 5,347,488 A · Semiconductor memory device for generating a controlling signal to select a word line

Abstract

A semiconductor memory device of the present invention comprises a memory cell group having a plurality of memory cells for storing data therein and a plurality of word lines each used to select a desired memory cell, a first signal line held at a first potential which enables the memory cells to operate sufficiently, a second signal line held at a second potential which enables a driver circuit to operate sufficiently, the driver circuit provided between the first signal line and the word lines, a decoder for receiving an address signal therein and for outputting access request signals each used to obtain access to a memory cell designated by the received address signal, at least one driving signal generator for receiving one of the access request signals therein and supplying a driving signal having the second potential of the second signal line to the driver circuit so as to activate the driver circuit, a first booster operated in response to the turning on of a power source so as to set the second signal line to the second potential, and a second booster operated in response to the generation of the access request signal so as to set the second signal line to the second potential.

Claims18

Dependent claims

A semiconductor memory device for generating a control signal to select a word line, comprising:

a memory cell for storing data therein;
a word line coupled to said memory cell;
a first voltage line for providing a first signal having a first potential level;
a word line activation circuit coupled to said word line and said first voltage line, for supplying said first signal from said first voltage line to said word line in response to a control signal;
a second voltage line for providing a second signal having a second potential level;
a control circuit coupled to said second voltage line and said word line activation circuit, for outputting said control signal in response to an activation signal, said control signal having a potential corresponding to said second potential level;
a first voltage supply circuit coupled to said second voltage line, for normally supplying a main voltage signal to said second voltage line to maintain said second voltage line at or above said second potential level;
and
a second voltage supply circuit coupled to said second voltage line, for supplying a compensation voltage signal to said second voltage line in response to said activation signal, in order to compensate said second voltage line at or above said second potential level.

6 more elements

A semiconductor memory device for generating a control signal to select a word line, comprising:

a memory cell for storing a data therein;
a word line coupled to said memory cell;
a first high voltage line for supplying a first boosted potential level;
a word line activation circuit coupled to said word line and said first high voltage line for supplying said first boosted potential level to said word line in response to a control signal;
a second high voltage line for supplying a second boosted potential level;
a control circuit coupled to said second high voltage line and said word line activation circuit for outputting said control signal in response to an activation signal, said control signal having a potential corresponding to said second boosted potential level;
a first boosting circuit coupled to said second high voltage line for normally boosting a potential level of said second high voltage line in order to maintain said second high voltage line at or above said second boosted potential level;
and
a second boosting circuit coupled to said second high voltage line for boosting the potential level of said second high voltage line in response to said activation signal in order to compensate the potential level of the second high voltage line.

6 more elements

A semiconductor memory device for generating a control signal to select a word line, comprising:

a memory cell for storing a data therein;
a word line coupled to said memory cell;
a first voltage line supplied a first potential level;
a word line activation circuit coupled to said word line and said first voltage line for supplying said first potential level to said word line in response to a control signal;
a second voltage line supplied a second potential level;
a control circuit coupled to said second voltage line and said word line activation circuit for outputting said control signal in response to an activation signal, said control signal having a potential corresponding to said second potential level;
a first voltage supplying circuit coupled to said second voltage line for supplying a voltage to said second voltage line in response to a clock pulse signal to maintain said second voltage line at or above said second potential level;
and
a second voltage supplying circuit coupled to said second voltage line for supplying a voltage signal to said second voltage line when said activation signal is supplied to said control circuit, to compensate the voltage on said second potential voltage line.

6 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device for generating a controlling signal to select a word line

Life of this patent

Semiconductor memory device for generating a controlling signal to select a word line

Life of this patent

Abstract

Claims18