Nonvolatile memory with blocked redundant columns and corresponding content addressable memory sets

A nonvolatile memory device comprising:

• (A) a main memory array for storing data, wherein the main memory array comprises:
• (1) a first block;
• (2) a second block;
• (B) a redundant memory array that comprises
• (1) a first redundant block that comprises a first redundant column of memory cells and a second redundant column of memory cells, wherein the first redundant block is associated with the first block of the main memory array and is selected when the first block is selected, wherein the first and second redundant columns of the first redundant block are used to replace defective columns of the first block;
• (2) a second redundant block that comprises a third redundant column of memory cells and a fourth redundant column of memory cells, wherein the second redundant block is associated with the second block of the main memory array and is selected when the second block is selected, wherein the third and fourth redundant columns of the second redundant block are used to replace defective columns of the second block;
• (C) a content addressable memory (CAM) that comprises
• (1) a first set of CAM cells associated with the first redundant column of the first redundant block and the third redundant column of the second redundant block for storing a first address of a first defective column in the main memory array;
• (2) a second set of CAM cells associated with the second redundant column of the first redundant block and the fourth redundant column of the second redundant block for storing a second address of a second defective column in the main memory array;
• (D) decoding means coupled to receive an incoming address from an external circuit for selecting (1) one of the first and second blocks for data access and (2) one of the first and second redundant blocks, wherein when the decoding means selects the first block, the decoding means selects the first redundant block, wherein when the decoding means selects the second block, the decoding means selects the second redundant block;
• and
• (E) comparison circuitry coupled between the CAM and the redundant memory array for comparing the address with the first and second redundant addresses, wherein the comparison circuitry activates the first and third redundant columns when the address matches the first address, wherein the comparison circuitry activates the second and fourth redundant columns when the address matches the second address, wherein the first set of CAM cells, the comparison circuitry, and the decoding means cause the first redundant column in the first redundant block to replace the first defective column when the first defective column is in the first block, wherein the first set of CAM cells, the comparison circuitry, and the decoding means cause the third redundant column in the second redundant block to replace the first defective column when the first defective column is in the second block, wherein the second set of CAM cells, the comparison circuitry, and the decoding means cause the second redundant column in the first redundant block to replace the second defective column when the second defective column is in the first block, wherein the second set of CAM cells, the comparison circuitry, and the decoding means cause the fourth redundant column in the second redundant block to replace the second column when the second defective column is in the second block.