Non-volatile associative memory with low transistor count

A non-volatile associative memory device including a plurality of memory cells, each of said memory cells comprising:

• first and second selecting transistors, a gate of said first selecting transistor and a gate of said second selecting transistor being connected to a word line, a drain of said first selecting transistor being connected to a first bit line, a drain of said second selecting transistor being connected to a second bit line;
• first and second non-volatile memory transistors for storing data in a non-volatile manner, a drain of said first non-volatile memory transistor being connected to a source of said first selecting transistor, a drain of said second non-volatile memory transistor being connected to a source of said second selecting transistor, a source of said first non-volatile memory transistor and a source of said second non-volatile memory transistor being connected to a source line, a gate of said first non-volatile memory transistor and a gate of said second non-volatile memory transistor being connected to a control gate line;
• and
• first and second output transistors, a drain of said first output transistor and a drain of said second output transistor being directly connected to a first output line, a source of said first output transistor and a source of said second output transistor being directly connected to a second output line, a gate of said first output transistor being connected to a drain of said first non-volatile memory transistor, a gate of said second output transistor being connected to a drain of said second non-volatile memory transistor.

A non-volatile associative memory device including a plurality of memory cells, each of said memory cells comprising:

• first and second selecting transistors, a gate of said first selecting transistor and a gate of said second selecting transistor being connected to a word line, a drain of said first selecting transistor being connected to a first bit line, a drain of said second selecting transistor being connected to a second bit line;
• first and second non-volatile memory transistors for storing data in a non-volatile manner, a drain of said first non-volatile memory transistor being connected to a source of said first selecting transistor, a drain of said second non-volatile memory transistor being connected to a source of said second selecting transistor, a source of said first non-volatile memory transistor and a source of said second non-volatile memory transistor being connected to a source line, a gate of said first non-volatile memory transistor and a gate of said second non-volatile memory transistor being connected to a control gate line;
• and
• first and second output transistors, a drain of said first output transistor and a drain of said second output transistor being connected to a first output line, a source of said first output transistor and a source of said second output transistor being connected to a second output line, a gate of said first output transistor being connected to a drain of said first non-volatile memory transistor, a gate of said second output transistor being connected to a drain of said second non-volatile memory transistor,
• wherein said memory cells are connected in series via said first and second output lines.