Method and apparatus for multiplying denormalized binary floating point numbers without additional delay

An apparatus for multiplying two binary floating point numbers, comprising:

• first and second exponent registers for storing the exponent values of first and second numbers;
• first and second fraction registers for storing the fraction fields of first and second numbers;
• first hidden bit logic means coupled to first exponent register for generating first hidden bit;
• second hidden bit logic means coupled to second exponent register for generating second hidden bit;
• first multiplier means coupled to first hidden bit logic means and second fraction register for multiplying first hidden bit and the fraction field of the second number producing hidden bit partial products;
• second multiplier means coupled to second hidden bit logic means and first fraction register for multiplying second hidden bit and the fraction field of the first number producing additional hidden bit partial products;
• third multiplier means coupled to first and second hidden bit logic means for multiplying first and second hidden bits producing additional hidden bit partial products;
• fourth multiplier means coupled to first and second fraction registers for multiplying the fraction fields of first and second numbers producing additional hidden bit partial products;
• a multiplier tree comprising a plurality of tree slices coupled to fourth multiplier means for receiving and summing partial products according to their binary weights, each tree slice comprising a plurality of bit adders hierarchically arranged into a plurality of processing levels;
• the multiplier tree further coupled to first, second, and third multiplier means for receiving into the tree slices the hidden bit partial products according to their binary weights after receiving the partial products from the fourth multiplier means, the tree slices comprising additional bit adders for receiving and summing all hidden bit partial products with the summed partial products to produce first and second sums, the number of levels of all bit adders being equal to or less than the number of levels needed for summing only the partial products;
• a bit adder coupled to the multiplier tree for receiving and summing first and second sums and producing a final product of first and second numbers;
• and
• a result register coupled to the bit adder for storing the final product.

A multiplier tree for summing M.sub.1 through M.sub.y subsets of partial products, each subset containing m partial products resulting from a multiplication of two binary operands, the multiplier tree comprising:

• T.sub.1 through T.sub.y tree slices, each T.sub.i tree slice for 1.ltoreq.i.ltoreq.(y-2) coupled to tree slices T.sub.i+1, T.sub.i+2, tree slice T.sub.y-1 coupled to tree slice T.sub.y, and tree slice T.sub.y coupled internally, and receiving the M.sub.i subset partial products of equal weight along an input bus, and including L.sub.1 through L.sub.z levels of bit adders, each L.sub.j level for 1.ltoreq.j.ltoreq.z for adding a m.sub.i,j subset of partial products comprising:
• p.sub.i,j counter blocks each having n inputs, where n is a positive integer, coupled to receive n partial products of the m.sub.i,j partial products and having x outputs, p.sub.i,j equal to the integer component of ((m.sub.i,j +1)/n), for summing the n partial products producing x output bits, each p.sub.i,j counter block in each level L.sub.j in each tree slice T.sub.i for 1.ltoreq.i.ltoreq.(y-n+2) coupled to a p.sub.i+1,j counter block and a p.sub.i+2, j counter block to apply carry out bits;
• s.sub.i,j carry-save adders, s.sub.i,j equal the greate of either zereo or the integer component of (((m.sub.i,j -p.sub.i,j *n)+1)/3), each carry-save adder coupled to receive as inputs three partial products of the m.sub.i,j partial products, for summing the three partial products producing two output bits, the s.sub.i,j carry-save adders in each level L.sub.j in each tree slice T.sub.i coupled to a s.sub.i+1,j carry-save adder to apply carry out bits;
• W.sub.i,j wires, w.sub.i,j equal to the greater of either zero or (m.sub.i,j- p.sub.i,j *n-s.sub.i,j * 3), each wire coupled to transmit one partial product of the m.sub.i,j partial products to a carry save adder in tree slice T.sub.i in level L.sub.j+1 where there is output from each level L.sub.j, m.sub.i,j partial products, m.sub.i,j equal to (s.sub.i,j +w.sub.i,j +s.sub.i,j-1);
• where at level L.sub.2, the m.sub.i,j partial products equals (m.sub.i,j +2);
• where each p.sub.i,j counter block further comprises d adder delays, wherein if equals a multiple of the d, then the m.sub.i,j partial products output from level L.sub.j includes
• (p.sub.i,j-d+1 +p .sub.i-1,j-d+1 +p.sub.i-2,j-d+ 1) additional partial products;
• and
• if j equals a multiple of d, minus 1, then the m.sub.i,j partial products output from level L.sub.j includes
• (m.sub.i,j +p.sub.i-2,j-d+1 -p.sub.i-1,j-d+1) additional partial products.

An apparatus for multiplying a first and second binary floating point numbers, each number having an exponent and a fraction, comprising:

• a hidden bit partial product generator for receiving the first and second numbers for generating hidden bit partial products dependent on the exponents of the first and second numbers;
• a partial product generator for receiving the first and second numbers for generating partial products of the fraction fields of the first and second numbers;
• a multiplier tree coupled to the partial product generator for receiving and summing the partial products according to their binary weights, and further coupled to the hidden bit partial product generator for receiving the hidden bit partial products after receiving the partial products, and summing the hidden bit partial products together with the partial products,and producing first and second sums;
• and
• a bit adder coupled to the multiplier tree for summing the first and second sums and producing a final sum equal to the product of the fraction fields of the first and second numbers.