Output circuit of PWM inverter
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsKazuyuki Takada, Toru Kishi
Life of this patent
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Abstract
An inexpensive output circuit of a PWM inverter for PWM controlling a coil voltage of a motor with small control error of voltage at a motor winding terminal and low power consumption includes an N channel power MOS-FET, a P channel power MOS-FET, a current control circuit 1 having a current output terminal, and a current control circuit 2 having a current input terminal. A current flowing out from the current output terminal of the current control circuit 1 and a current flowing in from the current input terminal of the current control circuit 2 are subjected to particular control to thereby control the N channel power MOS-FET and the P channel power MOS-FET.
Claims24
An output circuit of a PWM inverter comprising:
- a first power MOS-FET of N channel type, a second power MOS-FET of P channel type, and first, second, third and fourth diodes;
- current control means 1 including a current output terminal and for controlling a current flowing out from said current output terminal;
- current control means 2 including a current input terminal and for controlling a current flowing in from said current input terminal;
- and
- a DC main power supply;
- said first power MOS-FET having a drain connected to a cathode of said third diode;
- said third diode having an anode connected to a cathode of said first diode and a positive terminal of said DC main power supply;
- said second power MOS-FET having a drain connected to an anode of said fourth diode;
- said fourth diode having a cathode connected to an anode of said second diode and a negative terminal of said DC main power supply;
- said first power MOS-FET having a source connected to an anode of said first diode, a source of said second power MOS-FET and a cathode of said second diode;
- said first power MOS-FET having a gate connected to a gate of said second power MOS-FET, said current output terminal of said current control means 1 and said current input terminal of said current control means 2;
- a resistor and voltage limit means having a zener phenomenon for a positive and negative bidirectional voltage being connected in parallel between said gate and source of said first or second power MOS-FET;
- said current control means 1 and 2 having:
- a first state in which a current flowing out from said current output terminal of said current control means 1 is a first current value and a current flowing in from said current input terminal of said current control means 2 is a seventh current value;
- a second state in which a current flowing out from said current output terminal of said current control means 1 is a second current value and a current flowing in from said current input terminal of said current control means 2 is an eighth current value;
- a third state in which a current flowing out from said current output terminal of said current control means 1 is a fifth current value and a current flowing in from said current input terminal of said current control means 2 is a third current value;
- a fourth state in which a current flowing out from said current output terminal of said current control means 1 is a sixth current value and a current flowing in from said current input terminal of said current control means 2 is a fourth current value;
- and
- a fifth state in which a current flowing out from said current output terminal of said current control means 1 is a ninth current value and a current flowing in from said current input terminal of said current control means 2 is also said ninth current value;
- said first current value being larger than said seventh current value;
- said second current value being larger than said eighth current value;
- said third current value being larger than said fifth current value;
- said fourth current value being larger than said sixth current value;
- a different between said first current value and said seventh current value being larger than a difference between said second current value and said eighth current value;
- a difference between said third current value and said fifth current value being larger than a difference between said fourth current value and said sixth current value;
- said first state capable of proceeding to only said second and fifth states;
- said second state capable of proceeding to only said third and fifth states;
- said third state capable of proceeding to only said fourth and fifth states;
- said fourth state capable of proceeding to only said first and fifth states;
- and
- said fifth state capable of proceeding to at least said first and third states.
An output circuit of a PWM inverter comprising:
- a first power MOS-FET of N channel type and a second power MOS-FET of P channel type;
- current control means 1 including a current output terminal and for controlling a current flowing out from said current output terminal;
- current control means 2 including a current input terminal and for controlling a current flowing in from said current input terminal;
- and
- a DC main power supply;
- said first power MOS-FET having a drain connected to a positive terminal of said DC main power supply;
- said second power MOS-FET having a drain connected to a negative terminal of said DC main power supply;
- said first power MOS-FET having a source connected to a source of said second power MOS-FET, said first power MOS-FET having a gate connected to a gate of said second power MOS-FET, said current output terminal of said current control means 1 and said current input terminal of said current control means 2;
- a resistor and voltage limit means having a zener phenomenon for a positive and negative bidirectional voltage being connected in parallel between said gate and source of said first or second power MOS-FET;
- said current control means 1 and 2 having:
- a first state in which a current flowing out from said current output terminal of said current control means 1 is a first current value and a current flowing in from said current input terminal of said current control means 2 is a seventh current value;
- a second state in which a current flowing out from said current output terminal of said current control means 1 is a second current value and a current flowing in from said current input terminal of said current control means 2 is an eighth current value;
- a third state in which a current flowing out from said current output terminal of said current control means 1 is a fifth current value and a current flowing in from said current input terminal of said current control means 2 is a third current value;
- a fourth state in which a current flowing out from said current output terminal of said current control means 1 is a sixth current value and a current flowing in from said current input terminal of said current control means 2 is a fourth current value;
- and
- a fifth state in which a current flowing out from said current output terminal of said current control means 1 is a ninth current value and a current flowing in from said current input terminal of said current control means 2 is also said ninth current value;
- said first current value being larger than said seventh current value;
- said second current value being larger than said eighth current value;
- said third current value being larger than said fifth current value;
- said fourth current value being larger than said sixth current value;
- a different between said first current value and said seventh current value being larger than a difference between said second current value and said eighth current value;
- a difference between said third current value and said fifth current value being larger than a difference between said fourth current value and said sixth current value;
- said first state capable of proceeding to only said second and fifth states;
- said second state capable of proceeding to only said third and fifth states;
- said third state capable of proceeding to only said fourth and fifth states;
- said fourth state capable of proceeding to only said first and fifth states;
- and
- said fifth state capable of proceeding to at least said first and third states.
An output circuit of a PWM inverter comprising:
- a first power MOS-FET of N channel type, a second power MOS-FET of P channel type, and first, second, third and fourth diodes;
- current mirror means 1 including a current flowing-in terminal and first and second current flowing-out terminals and which functions to flow out from said first current flowing-out terminal a current in association with a current flowing out from said second current flowing-out terminal;
- current control means 3 including a current input terminal and for controlling a current flowing in from said current input terminal;
- current control means 2 including a current input terminal and for controlling a current flowing in from said current input terminal;
- a DC main power supply;
- and
- a first DC power supply having a negative terminal connected to a positive terminal of said DC main power supply;
- said first power MOS-FET having a drain connected to a cathode of said third diode;
- said third diode having an anode connected to a cathode of said first diode and the positive terminal of said DC main power supply;
- said second power MOS-FET having a drain connected to an anode of said fourth diode;
- said fourth diode having a cathode connected to an anode of said second diode and a negative terminal of said DC main power supply;
- said first power MOS-FET having a source connected to an anode of said first diode, a source of said second power MOS-FET and a cathode of said second diode;
- said first power MOS-FET having a gate connected to a gate of said second power MOS-FET, said first current flowing-out terminal of said current mirror means 1 and said current input terminal of said current control means 2, said second current flowing-out terminal of said current mirror means 1 being connected to said current input terminal of said current control means 3;
- said first DC power supply having a positive terminal connected to said current flowing-in terminal of said current mirror means 1;
- a resistor and voltage limit means having a zener phenomenon for a positive and negative bidirectional voltage being connected in parallel between said gate and source of said first or second power MOS-FET;
- said current mirror means 1 and said current control means 2 having:
- a first state in which a current flowing out from said first current flowing-out terminal of said current mirror means 1 is a first current value and a current flowing in from said current input terminal of said current control means 2 is a seventh current value;
- a second state in which a current flowing out from said first current flowing-out terminal of said current mirror means 1 is a second current value and a current flowing in from said current input terminal of said current control means 2 is an eighth current value;
- a third state in which a current flowing out from said first current flowing-out terminal of said current mirror means 1 is a fifth current value and a current flowing in from said current input terminal of said current control means 2 is a third current value;
- a fourth state in which a current flowing out from said first current flowing-out terminal of said current mirror means 1 is a sixth current value and a current flowing in from said current input terminal of said current control means 2 is a fourth current value;
- and
- a fifth state in which a current flowing out from said first current flowing-out terminal of said current mirror means 1 is a ninth current value and a current flowing in from said current input terminal of said current control means 2 is also said ninth current value;
- said first current value being larger than said seventh current value;
- said second current value being larger than said eighth current value;
- said third current value being larger than said fifth current value;
- said fourth current value being larger than said sixth current value;
- a different between said first current value and said seventh current value being larger than a difference between said second current value and said eighth current value;
- a difference between said third current value and said fifth current value being larger than a difference between said fourth current value and said sixth current value;
- said first state capable of proceeding to only said second and fifth states;
- said second state capable of proceeding to only said third and fifth states;
- said third state capable of proceeding to only said fourth and fifth states;
- said fourth state capable of proceeding to only said first and fifth states;
- and
- said fifth state capable of proceeding to at least said first and third states.
An output circuit of a PWM inverter comprising:
- a first power MOS-FET of N channel type and a second power MOS-FET of P channel type;
- current mirror means 1 including a current flowing-in terminal and first and second current flowing-out terminals and which functions to flow out from said first current flowing-out terminal a current in association with a current flowing out from said second current flowing-out terminal;
- current control means 3 including a current input terminal and for controlling a current flowing in from said current input terminal;
- current control means 2 including a current input terminal and for controlling a current flowing in from said current input terminal;
- a DC main power supply;
- and
- a first DC power supply having a negative terminal connected to a positive terminal of said DC main power supply;
- said first power MOS-FET having a drain connected to the positive terminal of said DC main power supply;
- said second power MOS-FET having a drain connected to the negative terminal of said DC main power supply;
- said first power MOS-FET having a source connected to a source of said second power MOS-FET, said first power MOS-FET having a gate connected to a gate of said second power MOS-FET, said first current flowing-out terminal of said current mirror means 1 and said current input terminal of said current control means 2, said second current flowing-out terminal of said current mirror means 1 being connected to said current input terminal of said current control means 3;
- said first DC power supply having a positive terminal connected to said current flowing-in terminal of said current mirror means 1;
- a resistor and voltage limit means having a zener phenomenon for a positive and negative bidirectional voltage being connected in parallel between said gate and source of said first or second power MOS-FET;
- said current mirror means 1 and said current control means 2 having:
- a first state in which a current flowing out from said first current flowing-out terminal of said current mirror means 1 is a first current value and a current flowing in from said current input terminal of said current control means 2 is a seventh current value;
- a second state in which a current flowing out from said first current flowing-out terminal of said current mirror means 1 is a second current value and a current flowing in from said current input terminal of said current control means 2 is an eighth current value;
- a third state in which a current flowing out from said first current flowing-out terminal of said current mirror means 1 is a fifth current value and a current flowing in from said current input terminal of said current control means 2 is a third current value;
- a fourth state in which a current flowing out from said first current flowing-out terminal of said current mirror means 1 is a sixth current value and a current flowing in from said current input terminal of said current control means 2 is a fourth current value;
- and
- a fifth state in which a current flowing out from said first current flowing-out terminal of said current mirror means 1 is a ninth current value and a current flowing in from said current input terminal of said current control means 2 is also said ninth current value;
- said first current value being larger than said seventh current value;
- said second current value being larger than said eighth current value;
- said third current value being larger than said fifth current value;
- said fourth current value being larger than said sixth current value;
- a different between said first current value and said seventh current value being larger than a difference between said second current value and said eighth current value;
- a difference between said third current value and said fifth current value being larger than a difference between said fourth current value and said sixth current value;
- said first state capable of proceeding to only said second and fifth states;
- said second state capable of proceeding to only said third and fifth states;
- said third state capable of proceeding to only said fourth and fifth states;
- said fourth state capable of proceeding to only said first and fifth states;
- and
- said fifth state capable of proceeding to at least said first and third states.
An output circuit of a PWM inverter comprising:
- a first power MOS-FET of N channel type, a second power MOS-FET of P channel type, and first, second, third and fourth diodes;
- current control means 1 including a current output terminal and for controlling a current flowing out from said current output terminal;
- current mirror means 2 including a current flowing-out terminal and first and second current flowing-in terminals and which functions to flow in from said first current flowing-in terminal a current in association with a current flowing in from said second current flowing-in terminal;
- current control means 4 including a current output terminal and for controlling a current flowing out from said current output terminal;
- a DC main power supply;
- and
- a second DC power supply having a positive terminal connected to a negative terminal of said DC main power supply;
- said first power MOS-FET having a drain connected to a cathode of said third diode;
- said third diode having an anode connected to a cathode of said first diode and a positive terminal of said DC main power supply;
- said second power MOS-FET having a drain connected to an anode of said fourth diode;
- said fourth diode having a cathode connected to an anode of said second diode and the negative terminal of said DC main power supply;
- said first power MOS-FET having a source connected to an anode of said first diode, a source of said second power MOS-FET and a cathode of said second diode;
- said first power MOS-FET having a gate connected to a gate of said second power MOS-FET, said current output terminal of said current control means 1 and said first current flowing-in terminal of said current mirror means 2, said current output terminal of said current control means 4 being connected to said second current flowing-in terminal of said current mirror means 2;
- said second DC power supply having a negative terminal connected to said current flowing-out terminal of said current mirror means 2;
- a resistor and voltage limit means having a zener phenomenon for a positive and negative bidirectional voltage being connected in parallel between said gate and source of said first or second power MOS-FET;
- said current control means 1 and said current mirror means 2 having:
- a first state in which a current flowing out from said current output terminal of said current control means 1 is a first current value and a current flowing in from said first current flowing-in terminal of said current mirror means 2 is a seventh current value;
- a second state in which a current flowing out from said current output terminal of said current control means 1 is a second current value and a current flowing in from said first current flowing-in terminal of said current mirror means 2 is an eighth current value;
- a third state in which a current flowing out from said current output terminal of said current control means 1 is a fifth current value and a current flowing in from said first current flowing-in terminal of said current mirror means 2 is a third current value;
- a fourth state in which a current flowing out from said current output terminal of said current control means 1 is a sixth current value and a current flowing in from said first current flowing-in terminal of said current mirror means 2 is a fourth current value;
- and
- a fifth state in which a current flowing out from said current output terminal of said current control means 1 is a ninth current value and a current flowing in from said first current flowing-in terminal of said current mirror means 2 is also said ninth current value;
- said first current value being larger than said seventh current value;
- said second current value being larger than said eighth current value;
- said third current value being larger than said fifth current value;
- said fourth current value being larger than said sixth current value;
- a different between said first current value and said seventh current value being larger than a difference between said second current value and said eighth current value;
- a difference between said third current value and said fifth current value being larger than a difference between said fourth current value and said sixth current value;
- said first state capable of proceeding to only said second and fifth states;
- said second state capable of proceeding to only said third and fifth states;
- said third state capable of proceeding to only said fourth and fifth states;
- said fourth state capable of proceeding to only said first and fifth states;
- and
- said fifth state capable of proceeding to at least said first and third states.
An output circuit of a PWM inverter comprising:
- a first power MOS-FET of N channel type and a second power MOS-FET of P channel type;
- current control means 1 including a current output terminal and for controlling a current flowing out from said current output terminal;
- current mirror means 2 including a current flowing-out terminal and first and second current flowing-in terminals and which functions to flow in a current corresponding to a current flowing in from said second current flowing-in terminal, from said first current flowing-in terminal;
- current control means 4 including a current output terminal and for controlling a current flowing out from said current output terminal;
- a DC main power supply;
- and
- a second DC power supply having a positive terminal connected to a negative terminal of said DC main power supply;
- said first power MOS-FET having a drain connected to a positive terminal of said DC main power supply;
- said second power MOS-FET having a drain connected to the negative terminal of said DC main power supply;
- said first power MOS-FET having a source connected to a source of said second power MOS-FET, a gate of said first power MOS-FET being connected to a gate of said second power MOS-FET, said current output terminal of said current control means 1 and said first current flowing-in terminal of said current mirror means 2, said current output terminal of said current mirror means 4 being connected to said second current flowing-in terminal of said current mirror means 2;
- said second DC power supply having a negative terminal connected to said current flowing-out terminal of said current mirror means 2;
- a resistor and voltage limit means having a zener phenomenon for a positive and negative bidirectional voltage being connected in parallel between said gate and source of said first or second power MOS-FET;
- said current control means 1 and said current mirror means 2 having:
- a first state in which a current flowing out from said current output terminal of said current control means 1 is a first current value and a current flowing in from said first current flowing-in terminal of said current mirror means 2 is a seventh current value;
- a second state in which a current flowing out from said current output terminal of said current control means 1 is a second current value and a current flowing in from said first current flowing-in terminal of said current mirror means 2 is an eighth current value;
- a third state in which a current flowing out from said current output terminal of said current control means 1 is a fifth current value and a current flowing in from said first current flowing-in terminal of said current mirror means 2 is a third current value;
- a fourth state in which a current flowing out from said current output terminal of said current control means 1 is a sixth current value and a current flowing in from said first current flowing-in terminal of said current mirror means 2 is a fourth current value;
- and
- a fifth state in which a current flowing out from said current output terminal of said current control means 1 is a ninth current value and a current flowing in from said first current flowing-in terminal of said current mirror means 2 is also said ninth current value;
- said first current value being larger than said seventh current value;
- said second current value being larger than said eighth current value;
- said third current value being larger than said fifth current value;
- said fourth current value being larger than said sixth current value;
- a different between said first current value and said seventh current value being larger than a difference between said second current value and said eighth current value;
- a difference between said third current value and said fifth current value being larger than a difference between said fourth current value and said sixth current value;
- said first state capable of proceeding to only said second and fifth states;
- said second state capable of proceeding to only said third and fifth states;
- said third state capable of proceeding to only said fourth and fifth states;
- said fourth state capable of proceeding to only said first and fifth states;
- and
- said fifth state capable of proceeding to at least said first and third states.
Dependencies are inferred from the claim text.